Is it possible to Configure BLSP as SPI on DragonBoard820c?


Hi. I would like to configure a BLSP as SPI on the Dragonboard820c. Is this possible? What steps do I need to do?


Which one ?

BLSPs are configured in the device-tree (arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi), you can see that blsp1/spi0 and blsp2/spi5 are enabled. Note that each APQ8096 BLSP as zero or more QUP core (SPI/I2C block) which can be configured either as SPI or I2C.


Hi Loic,
I would like to configure either BLSP 10 or BLSP 11 as SPI. Which address do I use for either of these BLSPs?


BLSP10 is linked to GPIO 8,9,10,11, BLSP11 to GPIO 58,59,60,61, make sure these pins are not used/routed by any other subsystem before.

I don’t have the datasheet of the mapped register, so I don’t know their address, maybe you can deduct them from the ones described in the existing device tree (blsp1, blsp2).


Hi Loic,
Neither of the already configured BLSPs shows a /dev/spidevX device. I got /dev/spidev0.0 to show up for BLSP 10 with this:
blsp2_spi3: spi@075b8000{
compatible = “qcom,spi-qup-v2.2.1”;

device@0 {
compatible = “spidev”;
#address-cells = <1>;
#size-cells = <1>;
reg = <0>; /* Chip select 0 */
spi-max-frequency = <19200000>;
Do you know what the reg <0> Chip select comment means? I just found this in an example, but no explanation.


By default spi bus is not available to userspace. It is possible to expose them by creating a special ‘spidev’ device slave node. You can add spidev inside the spi you want to expose.

This is the chip select address/idx of device. Usually 0. CS pin is enabled when master sends data to the slave(s).

You can also follow the following guide to enable spidev at runtime on LS connector:

On DB820C:

git clone
cd dt-update
sudo scripts/db820c/


Hi Loic,
Thank you for the information! Once I see the /dev/spidevX device I can open/read/write to the device, similar to the example program?


yes, you can use spidev uapi.