Device tree for I2S0 on Hikey 960



I didn’t have to make any changes specifically. But I made change to add sound/soc/hisilicon/hisi-i2s-plat.c to Makefile. With that I was able to see /snd/dev/xxxxx - both I2S devices.

Later I added changes to support saving parameters for multiple I2S devices which is about changing following fields in struct hisi_i2s in sound/soc/hisilicon/hisi-i2s.c
int rate;
int format;
int bits;
int channels;
u32 master;
u32 status;

to array and corresponding changes.


Thanks, I will try that.


Were you successful getting mono stream (1 channel) through I2S?


This is what they told me regarding setting it to mono; (see the last message from Tanglei)

I didn’t actually test it though, as you can see from the thread, that recommendation was made nearly 2 months after I initially filed the report. As such I had already worked around that issue in my Android HAL by just ignoring the second channel on incoming data, and filling it with bogus data on the outgoing stream.

16k and mono eh? Sounds like you’re working with voice.

Feel free to take a peek at how I dealt with voice.

And note that I also had to do rate conversion, because USB sound cards don’t offer 8 or 16k as options. The real meat is in this function;


If you want to change the sample rate to 16k,
u can have a try like this:

modify clk config:

  • #define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff000f
  • #define HI_ASP_CFG_R_CLK4_DIV_SEL 0x00ff002d


@guodong : Is it possible to obtain MCLK/SCLK output for I2S0 from anywhere on this board?


@doitright Do you mean this pin “GPIO_194_I2S0_XCLK”? If yes, according to the spec [1], the only way you get access to it is through J2002, the low-speed expansion connector.



No, that is not what I mean. That is just the bit clock.

MCLK will be several times higher in frequency than bit clock and will be the clock from which the bit clock is divided off of.


Hi @guodong,

As far as I can see from the Hi3660 App Processor Datasheet, MCLK is exposed by some pins on the SoC but it is not clear of what pin it is. Below note makes it clear,

On page 55,

In master mode, the AP side of Hi3660 generates the clock and sampling rate. In slave mode, the AUDIO_CODEC side generates the clock and sampling rate.

I assume that in the above note, clock refers to MCLK and sampling rate refers to Bit clock. In the schematic, we can see only the bit clock on GPIO_194_I2S0_XCLK and not MCLK anywhere.



I read that as bit clock and frame sync clock. Master clock will be about 8x or more of bit clock.

I think that this line (117) is actually setting up the master clock (the following 2 lines set up the bit and frame clocks):

The only question is whether we can get access to that master clock.


Now HiFi DSP is open and available on Hikey960 under AOSP source tree, someone may be interested to send audio data directly from DSP to I2S0.


Hi, I want to use max98357a as a codec. How can I define node about it in dts?


According to the datasheet, it’s a pretty simple device. Since i2s0 has a dummy codec on it already, you shouldn’t have to do anything, just plug it in.

The only thing you need to be aware of is that that device is not compatible with 1.8 volt I/O, so you will need a level shifter.


I get a error : reference to non-existent node or lable “max98357a” . How can I resolve it?


You didn’t listen. Like I said, DON’T DO ANYTHING. Just physically plug it in and it will work. Whatever you changed in the kernel, UNDO IT.


I use Linux system. There is no sound card. I add sound card, but there is no BCLK signal. How can I resolve it?


I2S0 was enabled in this commit;

BCLK will be off until you play some sound (i.e. “tinymix 48kHz.wav”)


BCLK is off when I play some sound.


And do you have that commit in your kernel?


Hi, doitright. I am in China. I cann’t open the website that you say. Can you copy it and paste it here?