Using OpenOCD with the Ultra96 JTAG adapter

Hi All,

I’m trying to use OpenOCD with the Ultra96 JTAG adapter. The adapter shows up as two USB serial ports on my system (this is expected) but I don’t know what protocol the serial to JTAG the adapter is using. If I have that then I can tell OpenOCD to use that as the interface.

If someone has already done this please let me know what interface you used.

Can’t give you the whole answer but…

Two serial ports means it is almost certainly based on one of the FTDI parts ( Interface Driver: ftdi in ). This will sort out the protocol but in addition to this you will need to understand how the buffer between the FTDI part and the JTAG socket has been configured.

Take a look at interface/ftdi/*.tcl to look for the sort of additional configuration that will be needed as well as the documentation above. Ideally you need a schematic diagram of the adaptor but if the buffer chip is “obvious” within the adaptor you might be able to figure things out with a bit of eyeballing and a multi-meter.

Thanks @danielt! I find that if I use the interface ftdi/digilent-h1.cfg and set adapter_hz to 1000 it gets a little further along. To get that to work though I modified the digilent-h1.cfg file to remove the identifier string. There are a BUNCH of adapters that all identify with the FTDI 0x0403:0x6010 VID/PID pair.

I suppose if I wanted to be super industrious I could reflash the FTDI2233H with the FTDI firmware from their web site. But before I do that I’ll get an extra adaptor so that I won’t be left high and dry without a working adapter for Vivado.

Further along as in the computer is talking to the programmer or further along as in the programmer is actually reading the JTAG ID from the target device?

It doesn’t actually talk to the JTAG pins as far as I can tell. In order to debug this further I need to figure out which pins are connected to the JTAG pins on the FT2333H chip, Then I could use the generic FTDI driver with the appropriate bit masks set and it should “just work” in terms of being able to see the JTAG taps. I downloaded the docs from the FTDI site on the MPSEE which describe how it works and I can see from the chip markings on the pod that is what chip they use.

I am also pursuing a simple script that will essentially do everything the Xilinx FSBL does when setting up an Ultrascale prior to jumping into the kernel so that I can debug things in the kernel from gdb on the workstation.