I think I may have accidentally connected (and powered) the AES-ACC-U96-JTAG board where it was misaligned by one pin. I’m trying to understand the consequences…
In looking at the Ultra96 board schematic, I see there is “JT1” device connected pin 4 of J1. What is that?
I think it is likely that the JTAG board’s GND pin was connected to VREF (pin 4) of the Ultra96…
Also, the JTAG/serial board now seems dead…
