The baudrate is also limited by the UART controller clock which is internally divided by 16 to generate the transmit clock (cf pl011 spec). With your result, that would mean the UART controller is fed with a 100MHz clock (6.25 * 16).
On the other side, looking deeper in hisilicon clock driver  we can see that:
UART3_CLK = CLK_PPLL0 / 16
CLK_PLL0 is defined at a fixed at 1600000000 (HZ) which gives 100MHz for UART3_CLK, matching the prediction.
So this explains the limitation. Now if you really want to reach 9Mb/s I assume this is a request for hisilicon (I suppose ‘fixed’ clock can be configured from bootloader).
If the baudrate is not in the following list, you need to use BOTHER (baudrate other).