Based on your description, it does sound like the DRAM clock, but as the chip enters power saving modes the DRAM clock will slow down. The Linux Debian builds do not yet implement all of the possible power savings modes on the 410, however the Android builds do. Have you tried building Android and putting it on the board?
The layouts for the 410c board and the eragon are very different. Since thisis an issue related to the eragon design, you should talk to eInfoChips about your issue and see if they can help. When we designed the 410c board we had emissions jamming the GPS, but we were able to resolve this with a shield over the 410, PMIC, and memory.
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