Setting up Vivado project for ultra96 and flashing


#1

So here are the steps I followed:

  • Installed Vivado 2018.1
  • Created a new RTL project
  • Left the Add Sources/Constraints blank
  • Selected Ultra96 in the Add Part section.
  • Created the following blocks
  • Zynq Ultrascale+ MPSoC
  • AIX GPIO
  • Ran Block/Connection Automation
  • Created HDL Wrapper for the design
  • Ran RTL-Elaborated Designed
  • Assigned all gpio_rtl_tri_io as INOUT and to pins sequentially from A2-E8
  • Generated Bitstream
  • Exported Hardware
  • Opened a ‘C’ Hello world template.

From that point on I have a couple of questions:

  1. Any instructions on flashing/deploying the project on the ultra96?
  2. Is there a pinout that tells what package pins are connected to the Low-Speed header?

Thanks!


#2

Do you have a Xilinx JTAG cable? I will write up some basic instructions, which are easiest if you can download directly to the board via JTAG.

Bryan


#3

Also, are you using the Seeed mezzanine for your USB-UART or do you have a dongle that you plan to connect to J6?

Bryan