So here are the steps I followed:
- Installed Vivado 2018.1
- Created a new RTL project
- Left the Add Sources/Constraints blank
- Selected Ultra96 in the Add Part section.
- Created the following blocks
- Zynq Ultrascale+ MPSoC
- AIX GPIO
- Ran Block/Connection Automation
- Created HDL Wrapper for the design
- Ran RTL-Elaborated Designed
- Assigned all gpio_rtl_tri_io as INOUT and to pins sequentially from A2-E8
- Generated Bitstream
- Exported Hardware
- Opened a ‘C’ Hello world template.
From that point on I have a couple of questions:
- Any instructions on flashing/deploying the project on the ultra96?
- Is there a pinout that tells what package pins are connected to the Low-Speed header?