The jumpers are installed.
In fact there is no physical component anywhere on the board, the EMBEDDED_SHORTING_BARs are just zero length copper tracks. We use this to force separate net names for the voltage supply, and the remote voltage sense nodes. If we just used one net for source and sense the CAD tool would join the sense pin to the supply node where the track is shortest, (at balls F7 and C8 under U9), but we want the Vsense ball to be sampling the voltage at the capacitor furthest from U9. We place JP2 right beside C58 and the CAD tool then routes a proper VSense track.
The Layout of the power systems for this chipset is very complex, make sure you simulate your layout as described in the Processor Design Guidelines, and meet all of the impedance requirements. If your CAD tool cannot do these simulations there are third parties that can do it for you (for a fee) such as www.valydate.com
Full Disclosure: I am an employee of Qualcomm Canada, any opinions I may have expressed in this or any other post may not reflect the opinions of my employer.