I used qemu to run optee and wrote some CA/TAs.
In recent days I want to keep optee to a non-simulated platform.So, I bought the Hikey960 development board from the internet, with a USB to TTL.
I follow some instructions:
https://github.com/96boards-hikey/tools-images-hikey960/blob/6769f8658ba2c286fe209c34365535e1f42bd0c5/recovery-flash-uefi.sh
https://github.com/OP-TEE/build/blob/master/hikey960.mk
make toolchains
make
make flash
succeeds
power the board, the output of sudo minicom -D /dev/ttyUSB0 115200 as follows:
hikey960 boarid:5301 xloader use UART6
scsysstat_value[0].
clear reset source
last_keypoint0,reboot_type0
secdbg not DCU.
SecDbgVer exit
xloader chipid is: 0x36600110, start at 363ms.
Build Date: Dec 6 2017, 15:31:59
[clock_init] ++
hikey960 [hikey960_clk_init]
hi3660 [clk_setup]
[clock_init] --
storage type is UFS
ufs retry: 6 count v_tx:0 v_rx:0
ufs set v_tx:0 v_rx:0
Hikey960[5301] no need avs_init.
ddr ft:0xf20332a3,mode:1 target:4
UceLdOk
density: 0x00080008,0x00080008,0x00080008,0x00080008,0x00080008,0x00080008,0x00
ddr info 0x00000401
400M
685M
1067M
C3R,V0x0000002e e:193
C0R,V0x0000002f e:66
C1R,V0x0000002e e:66
C3R,V0x0000002f e:66
C0R,V0x00000030 e:66
C1R,V0x0000002f e:66
C2R,V0x00000030 e:66
C3R,V0x00000030 e:66
C0R,V0x00000031 e:66
C1R,V0x00000030 e:66
C2R,V0x00000031 e:66
C3R,V0x00000031 e:66
C0R,V0x00000032 e:65
C1R,V0x00000031 e:65
C2R,V0x00000032 e:66
C3R,V0x00000032 e:66
C0R,V0x00000033 e:65
C1R,V0x00000032 e:65
C2R,V0x00000033 e:66
C3R,V0x00000033 e:65
C3R,V0x0000002e e:66
C3R,V0x0000002f e:66
C0R,V0x00000030 e:193
C2R,V0x0000002e e:66
C3R,V0x00000030 e:66
C0R,V0x00000031 e:66
C1R,V0x00000030 e:66
C2R,V0x0000002f e:66
C3R,V0x00000031 e:66
C0R,V0x00000032 e:66
C1R,V0x00000031 e:66
C2R,V0x00000030 e:66
C3R,V0x00000032 e:66
C0R,V0x00000033 e:65
C1R,V0x00000032 e:65
C2R,V0x00000031 e:66
C3R,V0x00000033 e:65
C0R,V0x00000034 e:65
C1R,V0x00000033 e:65
C2R,V0x00000032 e:65
C3R,V0x00000034 e:65
1244M
1866M
C1R,V0x00000015 e:66
C0R,V0x00000016 e:66
C1R,V0x00000016 e:66
C3R,V0x00000016 e:66
C0R,V0x00000017 e:66
C1R,V0x00000017 e:66
C2R,V0x00000017 e:66
C3R,V0x00000017 e:66
C2R,V0x00000014 e:113
C2R,V0x00000015 e:66
C1R,V0x00000016 e:66
C2R,V0x00000016 e:66
C3R,V0x00000016 e:66
C0R,V0x00000017 e:193
C1R,V0x00000017 e:66
C2R,V0x00000017 e:66
C3R,V0x00000017 e:66
pack0Idx0Dcc:0
pack1Idx0Dcc:0
pack2Idx0Dcc:1
pack3Idx0Dcc:0
iomcu_subsys_init
boot_c0 PROFILE 4
slave0 irq0:0x00000004
slave1 irq0:0x00000004
NOTICE: BL2: v1.4(release):v1.5-rc2
NOTICE: BL2: Built : 13:48:20, Jul 26 2018
NOTICE: ufs: H**** device must set VS_DebugSaveConfigTime 0x10
NOTICE: BL2: Booting BL31
NOTICE: BL31: v1.4(release):v1.5-rc2
NOTICE: BL31: Built : 13:48:21, Jul 26 2018
D/TC:0 add_phys_mem:526 TEE_SHMEM_START type NSEC_SHM 0x3ee00000 size 0x00200000
D/TC:0 add_phys_mem:526 TA_RAM_START type TA_RAM 0x3f200000 size 0x00e00000
D/TC:0 add_phys_mem:526 VCORE_UNPG_RW_PA type TEE_RAM_RW 0x3f046000 size 0x001b0
D/TC:0 add_phys_mem:526 VCORE_UNPG_RX_PA type TEE_RAM_RX 0x3f000000 size 0x00040
D/TC:0 add_phys_mem:526 CONSOLE_UART_BASE type IO_NSEC 0xffe00000 size 0x0020000
D/TC:0 verify_special_mem_areas:470 NSEC DDR memory [40000000 c0000000]
D/TC:0 verify_special_mem_areas:470 NSEC DDR memory [0 3e000000]
D/TC:0 add_va_space:565 type RES_VASPACE size 0x00a00000
D/TC:0 add_va_space:565 type SHM_VASPACE size 0x02000000
D/TC:0 dump_mmap_table:698 type IO_NSEC va 0x3b400000..0x3b5fffff pa 0xffe)
D/TC:0 dump_mmap_table:698 type TA_RAM va 0x3b600000..0x3c3fffff pa 0x3f2)
D/TC:0 dump_mmap_table:698 type SHM_VASPACE va 0x3c400000..0x3e3fffff pa 0x000)
D/TC:0 dump_mmap_table:698 type RES_VASPACE va 0x3e400000..0x3edfffff pa 0x000)
D/TC:0 dump_mmap_table:698 type NSEC_SHM va 0x3ee00000..0x3effffff pa 0x3ee)
D/TC:0 dump_mmap_table:698 type TEE_RAM_RX va 0x3f000000..0x3f045fff pa 0x3f0)
D/TC:0 dump_mmap_table:698 type TEE_RAM_RW va 0x3f046000..0x3f1fffff pa 0x3f0)
D/TC:0 core_mmu_entry_to_finer_grained:653 xlat tables used 1 / 5
D/TC:0 core_mmu_entry_to_finer_grained:653 xlat tables used 2 / 5
I/TC:
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[0] with top at 0x3f08aa38
D/TC:0 init_canaries:164 watch *0x3f08aa3c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[1] with top at 0x3f08b278
D/TC:0 init_canaries:164 watch *0x3f08b27c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[2] with top at 0x3f08bab8
D/TC:0 init_canaries:164 watch *0x3f08babc
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[3] with top at 0x3f08c2f8
D/TC:0 init_canaries:164 watch *0x3f08c2fc
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[4] with top at 0x3f08cb38
D/TC:0 init_canaries:164 watch *0x3f08cb3c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[5] with top at 0x3f08d378
D/TC:0 init_canaries:164 watch *0x3f08d37c
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[6] with top at 0x3f08dbb8
D/TC:0 init_canaries:164 watch *0x3f08dbbc
D/TC:0 init_canaries:164 #Stack canaries for stack_tmp[7] with top at 0x3f08e3f8
D/TC:0 init_canaries:164 watch *0x3f08e3fc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[0] with top at 0x3f08f038
D/TC:0 init_canaries:165 watch *0x3f08f03c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[1] with top at 0x3f08fc78
D/TC:0 init_canaries:165 watch *0x3f08fc7c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[2] with top at 0x3f0908b8
D/TC:0 init_canaries:165 watch *0x3f0908bc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[3] with top at 0x3f0914f8
D/TC:0 init_canaries:165 watch *0x3f0914fc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[4] with top at 0x3f092138
D/TC:0 init_canaries:165 watch *0x3f09213c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[5] with top at 0x3f092d78
D/TC:0 init_canaries:165 watch *0x3f092d7c
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[6] with top at 0x3f0939b8
D/TC:0 init_canaries:165 watch *0x3f0939bc
D/TC:0 init_canaries:165 #Stack canaries for stack_abt[7] with top at 0x3f0945f8
D/TC:0 init_canaries:165 watch *0x3f0945fc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[0] with top at 0x3f098
D/TC:0 init_canaries:167 watch *0x3f09663c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[1] with top at 0x3f098
D/TC:0 init_canaries:167 watch *0x3f09867c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[2] with top at 0x3f098
D/TC:0 init_canaries:167 watch *0x3f09a6bc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[3] with top at 0x3f098
D/TC:0 init_canaries:167 watch *0x3f09c6fc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[4] with top at 0x3f098
D/TC:0 init_canaries:167 watch *0x3f09e73c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[5] with top at 0x3f0a8
D/TC:0 init_canaries:167 watch *0x3f0a077c
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[6] with top at 0x3f0a8
D/TC:0 init_canaries:167 watch *0x3f0a27bc
D/TC:0 init_canaries:167 #Stack canaries for stack_thread[7] with top at 0x3f0a8
D/TC:0 init_canaries:167 watch *0x3f0a47fc
I/TC: OP-TEE version: 3.2.0 #1 2018��年 07��月 26��日 ��星��期�05:46:51 UTC aarch64
D/TC:0 tee_ta_register_ta_store:534 Registering TA store: 'REE' (priority 10)
D/TC:0 tee_ta_register_ta_store:534 Registering TA store: 'Secure Storage TA' ()
D/TC:0 mobj_mapped_shm_init:559 Shared memory address range: 3c400000, 3e400000
I/TC: Initialized
D/TC:0 init_primary_helper:917 Primary CPU switching to normal world boot
UEFI firmware (version Alpha built at 13:47:58 on Jul 26 2018)
then
Press ESCAPE for boot options .
Android Fastboot mode - version 0.7.
Press RETURN or SPACE key to quit.
I have not worked on a development board before.I have some questions:
- What is missing or wrong during my operation ?
- How can I run xtest or hello_world of optee ?
Thank you!
