New to programming in Quartus Prime. Trying to follow the directions from the post of programming fpga. Still get errors on generating - HDL (successful with errors), synthesis (successful with errors) but stops at the assembler due to ip not being registered on system. Want to go old school and select the closest chip set and do my own pin-map. Any suggestions of what the closest chip name is? Since C5AB******* is not even a choice under Cyclone V. Also, is there a better place to get the pin-map info than the schematic. Sometimes you get the pin, other times you get HPS reference. Thank you in advance for any help
When starting a new Quartus project, the part to be selected from the drop list is 6CSEBA6U19I7.
The released project includes few IPs that are not free.
The video IP from IntelPSG (Altera) and the SD card IP (interface to the WiFi module) that comes from SLS: http://www.slscorp.com/ip-cores/memory/sd-emmc-host-controller.html
You can contact SLS for an evaluation license.
When writing your own code without license for the above functions, you should disable them in QSYS (for any Quartos rev before 18.0, from 18.0 the tool name changed to Platform Designer)
Thanks for the response. Just to make sure I am tracking correct. Did not see 6CSEBA6U19I7 on my device list but did see ‘5CSEBA6U19I7’. That device did show up when I imported the CV96 project. Noticed it only had 45K logic elements – is there a way to have access to the full 110K elements? Or do I update my .qdz file from altera? The advice about the ips really help make sense of the error messages – thank you for the info. Guess working with SOCs is a bit different from FPGA strictly. Now going through the tutorial on rocketboard.org. Any suggestions of getting the pin out list for the fpga?