I2S MUX Register Description


#1

Hi,

Could someone provide detailed register description of following registers. I was not able to find them in the HRD document.

■ LPASS_CSR_GP_IO_MUX_SPKR_CTL (addr: 0x07702004)
■ LPASS_CSR_GP_IO_MUX_MIC_CTL (addr: 0x07702000)

Thanks

RD


#2

Does that code even work? E.g. in sound/soc/msm/msm8x16.c

    pdata->vaddr_gpio_mux_spkr_ctl =
            ioremap(LPASS_CSR_GP_IO_MUX_SPKR_CTL , 4);

The ioremap() is aligning the address on PAGE_MASK and the register may not be where you think. I haven’t checked the details, but it seems strange.

In the 4.9 kernel there is no longer any reference to the 0x07702000 register. Instead the 0x07708000 is defined in the device tree. And that register is present in the HW register document:
16.1 LPASS_LPA_IF
0x07708004 LPASS_LPAIF_HW_CONFIG

BR,
Nicklas


#3

I’m using embedded linux and the register is in the device tree apq8016-sbc.dtsi:

	sound: sound {
		compatible = "qcom,apq8016-sbc-sndcard";
		reg = <0x07702000 0x4>, <0x07702004 0x4>;
		reg-names = "mic-iomux", "spkr-iomux";

#4

Has then been any break through on these registers? I’m also working on a project that is using I2S and need to configure the system and these registers seem to be missing link for why I need to map the 4 internal I2S blocks to the 2 external I2S pins sets.