So there is no easy way to do this in userspace, usually, this is up to the kernel to perform cache maintenance if necessary (e.g. enqueueing/dequeuing dma video buffer). Some drivers also propose an interface to user-space via specific ioctls.
It’s also possible to access a restricted set of cache maintenance ops from userspace (EL0) with ARM64(aarch64). When UCI bit of the system control register is set, it enables EL0 access in AArch64 for
DC CVAU ,
DC CIVAC ,
DC CVAC , and
IC IVAU instructions . It allows you, for example, to perform a ‘clean & invalidate’ of a data cache line: dc civac, addr