I’m looking for a way to flush the L1 and L2 cache. I found the instruction " IC IALLUIS" but i have the feeling that his is only flushing the L1 instruction cache. Any idea’s ???
Which side (I$ or D$) and why?
Almost all cache management on ARMv8 is by virtual address; the concept of “just-drop-all-the-caches” may not even exist in some ARMv8 implementations. In practice there usually is some support since its needed for multi-cluster power management, however the cache flush process is not designed to be used for general purpose cache management:
Actually this one might be more helpful (and does include code to nuke the caches… whilst also telling you not do it):
I want to run a test for wich i have to flush atleast the instruction cache. This way the code has to be fetched from main memory again
I have seen that one. But what i don’ t understand is if it would flush both L1 and L2. Because only L1 has a separate data and instruction cache.
I have seen that one. But what i don’ t understand is if it would
flush both L1 and L2. Because only L1 has a separate data and
Depends which instructions you use but Hikey960 “to the
point of unification” means L1 only and "to the point of coherency"
means L1 and L2.
IC instructions only flush to the point of unification, so if you have
to flush the L2 you need to use the DC instructions and flush to the
point of coherency.
Thanks i used the code from the manual Cleaning to Point of Coherency. It’s seems to be working.