Error in i2c when communicating with device address 0x04, Is this address reserved by the qualcomm processor?

#1

I recently brought one Open-Q 2100 SOM which uses Snapdragon 2100 as the processor. Using this SOM I tried to connect with OVP921 through i2c bus 5 which has a device address of 0x04 and 0x05. OVP921 is using SCCB instead of i2c but they are almost similar in the protocol and both SOM and OVP921 have the same 1.8V as the I/O pin voltage rating. When we tried to communicate with OVP921 after sending the device address of the slave, that is 0x04, i2c communication become stopped by a stop signal with an error NACK: slave not responding, ensure its powered: msgs(n:2 cur:0 tx) bc(rx:1 tx:1) mode:FIFO slv_addr:0x4 MSTR_STS:0x0d1300c8 OPER:0x00000010.
As we checked the waveform of the i2c communication we got to know that the slave device, that is OVP921, makes ACK by pulling down the SDA to low at the 9th clock of SCL. Even though it is making ACK at the 9th clock SOM is detecting them as NACK. We connected the same OVP921 to an Arduino UNO through a 1.8v to 3.3v bidirectional voltage level shifter and the Arduino makes proper communication with OVP921 without any error. Other i2c device like ADV7533 are detecting by the SOM. I am attaching the waveform of the communication of SOM with OVP921. Could you please help me to sort out the issue.

The device address of OVP921 is 0x04 or 0x05(7bits 0x04 or 0x05,8bits 0x08 or 0x0A), Does these addresses are reserved by Qualcomm processors? And is that the reason for Qualcomm processor unable to communicate with OVP921?

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#2

Hi @Raptor

The waveform looks good to me and there does seem to be a correct ACK from something on the I2C bus. I do know that the Qualcomm proprietary I2C drivers at one time had some messyness concerning addresses being shifted one place, but I think these are the Linaro upstream drivers and I believe they are “normal”.

Are there any other devices on the I2C bus, or is it just the OVP921?

I notice during the 9th clock pulse the data goes to a slightly lower voltage, I usually see this when two devices are driving the bus at the same time, that is why I am asking about other devices on the bus.

I don’t believe that Qualcomm hardware has restrictions on any I2C address, so it ‘should’ work.

I am guessing you are running the Linux 4.19/5.0 kernel from Linaro and not the 3.18 kernel from Qualcomm, please confirm.

#3

To be honest I don’t think Linaro makes any kernels for Snapdragon 2100.

#4

@danielt is correct, I suspect that @Raptor will need to talk to Intrinsyc about this issue…

#5

Hi @ljking and @danielt, Thanks for your support

We are using the the Qualcomm proprietary I2C driver, i.e. the i2c adapter named i2c-msm-v2.

There is only one device in the bus the OVP921 which is connected to i2c-5 having address 0x04(can also be configured as 0x05).

I ran i2cdetect on all the buses and the results are as below:

msm8909w:/ # i2cdetect -r 1 0x04 0x07
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-1 using read byte commands.
I will probe address range 0x04-0x07.
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:             04 05 06 07
10:
20:
30:
40:
50:
60:
70:
msm8909w:/ # i2cdetect -r 3 0x04 0x07
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-3 using read byte commands.
I will probe address range 0x04-0x07.
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:             04 05 06 07
10:
20:
30:
40:
50:
60:
70:
msm8909w:/ # i2cdetect -r 4 0x04 0x07
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-4 using read byte commands.
I will probe address range 0x04-0x07.
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:             04 05 06 07
10:
20:
30:
40:
50:
60:
70:
msm8909w:/ # i2cdetect -r 5 0x04 0x07
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-5 using read byte commands.
I will probe address range 0x04-0x07.
Continue? [Y/n]
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00:             04 05 06 07
10:
20:
30:
40:
50:
60:
70:

In all the busses the address 04 05 06 07 are used. Any idea what these addresses represent? I suspect these addresses are reserved by Qualcomm processors. As the OVP921 is using address 0x04 (which is reserved) hence it is inaccessible. Please put your thoughts on this.

I am using 3.18 kernel from Qualcomm.

#6

I would talk to Intrinsyc to see if there is anything they can do about this. Failing that I would look at using a very small FPGA on the I2C bus to dynamically translate the address as it is passing from the CPU to the display. Small Lattice FPGAs are only pennies and only use uW of power. Another option is to add a SPI to I2C bridge chip but that is probably more cost and power than an FPGA.

#7

HI @ljking, Thank you for your prompt reply.

I are trying to avoid a hardware change. It will be great if we get a solution which is in the software side. Awaiting your response.

#8

Hi @Raptor, sorry if I have created some confusion, I no longer work for Qualcomm, and although I have worked with Intrinsyc, I have never worked for them. I will never have a SW solution for you. You really need to talk to Intrinsyc yourself.