eMMC in DDR mode fails to boot

Products Support HiKey
#1

We are trying to boot the Hikey(LeMaker version) board (2GB variant) using the eMMC high speed DDR mode, but unsuccessful.

Steps followed:
1. Added the property “mmc-ddr-1_8v” along with “cap-mmc-highspeed” in the file hi6220.dtsi.

Result:
The board fails to boot.

The output on the serial console is as below	
[    2.373839] mmc0: new DDR MMC card at address 0001
[    2.375966] ledtrig-cpu: registered to indicate activity on CPUs
[    2.377365] hidraw: raw HID events driver (C) Jiri Kosina
[    2.386906] usbcore: registered new interface driver usbhid
[    2.386945] usbhid: USB HID core driver
[    2.393723] mmcblk0: mmc0:0001 008G70 7.28 GiB 
[    2.395380] mmcblk0boot0: mmc0:0001 008G70 partition 1 4.00 MiB
[    2.396913] mmcblk0boot1: mmc0:0001 008G70 partition 2 4.00 MiB
[    2.398365] mmcblk0rpmb: mmc0:0001 008G70 partition 3 4.00 MiB
[    2.400818] mmcblk0: error -110 sending status command, retrying
[    2.400864] mmcblk0: error -110 sending stop command, original cmd response 0x900, card status 0x900
[    2.400883] mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0

Kindly let us know the procedure to set the eMMC DDR mode and boot the board successfully.

Thanks
Uthra

#2

hi Uthra,

we are also facing same issue.
can u tell me are you able to resolve this issue.
we noticed that, in boot loaders the board is booting in DDR mode. but in Linux kennel we are facing same issue.

if you are able to resolve the issue please let me know.

Thanks
sukesh

#3

This seems to be a good write up on how to get it working https://movr0.com/2017/09/18/96boards-hikey-emmc-hacks/

#4

Hello,
We are still not able to boot the Hikey board in eMMC DDR mode. The board fails to boot when it is reading the partition table. Our objective is to boot the board in DDR mode.

Has anybody faced the same issue with Hikey eMMC DDR mode booting?

#5

I followed @peter-griffin’s link: https://movr0.com/2017/09/18/96boards-hikey-emmc-hacks/, I can use below DT binding for increasing mmc clock. But I also can confirm the eMMC DDR mode cannot work with dt property: mmc-ddr-1_8v, so file one bug for tracking this: https://bugs.96boards.org/show_bug.cgi?id=673.

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index 2b52630..2ad12ec 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -302,6 +302,8 @@
 			non-removable;
 			bus-width = <0x8>;
 			vmmc-supply = <&ldo19>;
+			mmc-hs200-1_8v;
+			max-frequency;
 		};
 
 		dwmmc_1: dwmmc1@f723e000 {
#6

Hi, I am the author of the website above (movr0.com)

Your binding for max-frequency is incorrect. The DesignWare MMC controller and hi6220 SoC only support a maximum frequency of 150MHz. According to the JEDEC eMMC specification, DDR mode supports a clock up to 52MHz. I’d advise you to enable and use HS200 mode over DDR mode, as the data transfer rate is much higher. If you wish to use DDR mode instead, I’d advise you to use the following bindings:

max-frequency = <52000000>;
mmc-ddr-1_8v;

If you wish to enable HS200 instead, please try the following bindings:

max-frequency = <150000000>;
mmc-hs200-1_8v;

I am not sure what affect using the binding max-frequency without a frequency has, but I’d imagine that would cause issues or be ineffective. I hope this helps. Please see my patch here for more information:
https://patchwork.kernel.org/patch/10171095/

Update: After further investigation, I am receiving the same issue as you. The device does not boot and reports several errors.

1 Like
#7

Hi,
We observed that, DDR 4-bit mode is working while lot of debug messages are inserted.
However, the DDR 8-bit mode is not working until now.

The booting summary table for Hikey board is shared below for reference.

| eMMC | Capacity| SDR | DDR-4bit | DDR-8bit | HS200 - 200MHz |
| v 4.5 | 64 GB | PASS | Not tested | FAIL | PASS |
| v 5.0 | 4 GB | PASS | Not tested | FAIL | PASS |
| v 5.1 | 8 GB | PASS | PASS | FAIL | FAIL |

#8

Hi All,
We are continuing our investigation of DDR 8-bit mode on Hikey Board by taking the register dumps.
We found that the “TBBCNT” register value in SDR mode and DDR 8-bit mode are very different during read operation after its setting.

The “TBBCNT” register value in SDR mode is 0x00001000 whereas in DDR 8-bit mode it gets set to 0x00000000 during read operation.

Please find the register dump values as below for reference

“In case of SDR mode”
============== REGISTER DUMP ==============
[ 2.185569] : FIFOTH: 0x607f0080
[ 2.185579] : TCBCNT: 0x00001000
[ 2.185589] : TBBCNT: 0x00001000
[ 2.185599] : HCON: 0x00c424c1
[ 2.185609] : UHS_REG: 0x00000000

“In case of DDR 8-bit mode”
============== REGISTER DUMP ==============
[ 2.544202] : FIFOTH: 0x10030004
[ 2.544205] : TCBCNT: 0x00000200
[ 2.544207] : TBBCNT: 0x00000000
[ 2.544209] : HCON: 0x00c424c1
[ 2.544211] : UHS_REG: 0x00010000

Does anyone have the idea, why in DDR 8-bit mode the “TBBCNT” register value is getting set to 0x00000000?

Thanks
Uthra

#9

I’ve been working on this issue with limited success. I am far from an expert in this area, but playing around with the bus clock, I was able to initialize the eMMC in DDR52 mode without any errors. I set the bus clock to around ~51MHz with a divisor of 1, so the actual clock was ~25-26MHz (according to the driver.) I have not had success by hardcoding this value into the dw_mmc-k3 driver. I don’t have an oscilloscope, but will continue to work on this issue to the best of my ability.

#11

Hi,
Thanks a lot… with your recommendation of modifying the bus clock with a divisor of 1, we were able to initialize and boot the Hikey board in eMMC DDR mode…

Thanks
Uthra

#12

I’m glad it worked. How did you end up setting the bus clock? Did you hardcode it into the driver?

EDIT: I am preparing a patch for the controller driver and will post it here once tested thoroughly.

EDIT 2: https://github.com/oscardagrach/hikey-linux/commit/79b554876bfaf28433268b5796062cd99264f78a

I have tested this patch successfully with 8-bit DDR52 mode and a 52MHz clock. A clock divisor of 1 is required by the controller. According to comments on an old kernel driver for the hi6220 chipset, the controller is internally fixed to 2:1 divider in 8-bit DDR52 mode.