Does HiKey board supports PL310 cache controller?


#1

Hi,

I know that HiKey board has Cortex A53 core. Based on ARM v8 specification, it may comes with a PL310 cache controller or some co-processor that supports the similar cache lockdown functionality on ARM A7.

Does anyone know if HiKey board supports the cache lockdown functionality?

Thank you very much!


#2

Hi @nwpupanda,

The PL310 is an outer L2 cache controller, but CA53 on HiKey use internal L2 cache controller within cluster.

We are not sure L2 cache can be locked down in CA53 on HiKey:

From the ARMv8’s architecture reference manual “D3.4.10: Cache lockdown” says:
“The concept of an entry locked in a cache is allowed, but not architecturally defined.
How lockdown is achieved is IMPLEMENTATION DEFINED and might not be supported by: An implementation; or Some
memory attributes.”

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.architecture.reference/index.html

By checking CA53’s TRM documentation bellow, which doesn’t clearly define cache if it can support lockdown operations.

(CA57 explicitly defines NOT to support cache lockdown).

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500f/DDI0500F_cortex_a53_r0p4_trm.pdf