DDR3 page size tweaking


#1

Friends,

I am new to this game. I would like to do some tweaking of a board with DDR3 interface. Could someone suggest how I could change the page size for the DRAM on DDR3?

Or a way to confirm that the page size by default is 1024words. OR a way to tweak the firmware to make it 512 words?

Any documentation you can guide me to would also be awesome. Much appreciated.

Thanks,
K


#2

DDR setup is done very early in boot. If you’re asking on a public forum, you don’t have access to the source :wink:


#3

Thanks Joel, you are right. I guess its done in firmware somewhere. Bottomline what I was trying to get at was - its possible without redesgning a full SoC through the Fab.

Any pointers on where I should look next for the “very early in boot” stage, are appreciated.

Thanks!


#4

This is an exercise best done with a Lauterbach JTAG debugger. You don’t have source, nor symbols, nor debug scripts, so you would need to be comfortable with assembler.

DDR setup/init/training happens early in boot, which executes from a region of static RAM.

In order to debug via JTAG you need to know what cores/types are involved in the boot chain, in order to attach and step through it all.

JTAG is exposed on the Dragonboard.


#5

Another thought the DDR is auto-detected based on JEDEC standards. JDEC provides part config/info, then device is trained. Why on earth do you want to fool with DDR settings of a known working system?