DB410c: How to increase SPI performance

Products Support DragonBoard410c
#1

Hi Support Team,

We would like to improve the SPI performance with Dragonboard410.

Below is, SPI -Clock waveform. Speed is 50MHz.

SPI_Byte_Transfer_delay
SPI_Byte_Transfer_delay863×266 21.8 KB

Bit cycle = 20ns
BYTE transfer = 170nS + 80nS wait , each BYTE we have an idle time 80ns.
So TOTAL Byte cycle is actually 250nS.

Causing the Byte transfer to be 250 nS instead of 160 nS.

Our SPI configuration

blsp_dma: dma@7884000 {
         compatible = "qcom,bam-v1.7.0";
         reg = <0x07884000 0x23000>;
         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
         clock-names = "bam_clk";
         #dma-cells = <1>;
         qcom,ee = <0>;
         status = "disabled";
 };
blsp_spi1: spi@78b5000 {
         compatible = "qcom,spi-qup-v2.2.1";
         reg = <0x078b5000 0x600>;
         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
                  <&gcc GCC_BLSP1_AHB_CLK>;
         clock-names = "core", "iface";
         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
         dma-names = "rx", "tx";
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&spi1_default>;
         pinctrl-1 = <&spi1_sleep>;
         #address-cells = <1>;
         #size-cells = <0>;
         status = "disabled";
 };

How can we increase the performance of the SPI?

Thanks,
Darshak

#2

How do you perform the transfer? is it from user-space? what is the size you transfer each time? Could increasing the word size for you transfer be a possibility?

#3

@Loic We are sending data over SPI based LCD (resolution is 320x240) using frame buffer kernel driver - st7789. We are sending bulk transfer data (2403202(16bit) = 153600Bytes) over SPI.

-Darshak

#4

Could you check BAM/DMA mode is actually used for transfers (e.g. by adding a debug msg in spi_qup_do_dma function of spi-qup driver).

#5

@Loic, We have already enabled BAM/DMA mode and its working fine. We would like to reduce the wait time between the each Byte transfer. Current wait time is 80ns, we reduce it to 0ns. We wants like to enable the Multi transfer mode in SPI.

image
image740×239 37 KB

I am looking into, How to configure the multimaster mode in SPI?

-Darshak

#6

Well multi-transfer is supposed to work since all the transferred bytes should happen without CS change, however I’m not sure we can eliminate this 80ns hold time which could be due to hardware limitation. I don’t see anything in the driver supposed to configure this.

#7

Our scenario is, We are sending the single frame data 153600 (240 * 320 * 2Bytes) to SPI-LCD. Our SPI CLK Speed is 50MHz. As per calculation 1FPS = 240x320x16bit*(1/50MHz) = ~27ms/frame

Due to this 80ns wait time in SPI each Byte transfer, Actual time is increase 153600 * 250ns = 38.40ms. If we reduce this 80ns wait time to 0, we should get 250ns - 80ns = 153600 * 170ns = 26.12ms.

I am referring the document “lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf” and section SPI timing definitions.

Also checking with ** num-cs ** driver file: drivers/spi/spi-qup.c" 1282 lines
image

However, No changes seen in the wait time.

-Darshak

#8

Well it’s not clear how to enable the ‘compressed’ method. You can try the following change, but I’ve not tested it:

diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
index dd3434a..0894e91 100644
--- a/drivers/spi/spi-qup.c
+++ b/drivers/spi/spi-qup.c
@@ -785,6 +785,8 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
        else
                control &= ~SPI_IO_C_CLK_IDLE_HIGH;
 
+       control |= SPI_IO_C_MX_CS_MODE;
+
        writel_relaxed(control, controller->base + SPI_IO_CONTROL);
#9

I have tried with your suggestion, some other trial. However, I am not getting succeed to reduce the wait time.

-Darshak