Clk pin for RTL on ultra96v2

Products Support Ultra96
#1

Hello,

Been looking around various forums and I can’t seem to find a direct answer to the question.

If one is doing a pure RTL design on the 96 board is there no clock pin?
I can’t seem to find anything clear in the constraints file - online tutorials and blogs suggest that you have to grab the clock off the zync feed it to a clocking wizard and then go through the whole rigamarole of Vitis & fur- I mean bootloaders XD

I’ve gotten the above to work but it’s rather convoluted, just for a clk.

Thanks,
-L

#2

Hello L,

Ultra96 was always intended to be used as a hybrid system, with both the PS and PL. In other design examples, PL clocks are derived from the PS clock. There is no separate, PL-only oscillator on the board.

Are you interested in attaching an external oscillator to a clock capable pin on the expansion connectors?

For RTL-only designs, you might be better suited with something like the Arty-S7 (http://avnet.me/artys7).

Bryan

#3

Oh eventually I will be integrating in the hardcore processors, but in terms of debugging the RTL it just adds hassle having go into SDK and all + the time to synth added block design.

External clk would I suppose be the only option then. Do you have any recommendations?

Thanks,

  • L
#4

Look for anything with “GC” or “HDGC” in the Xilinx pin name attached to the expansion connectors. The GC stands for Global Clock and the HDGC is a Global Clock on a High Density bank. For example, you have access to all of the following MPSoC pins through the expansion connectors:
E8, D8, D7, D6, D5, C5, L1, L2

The latest v1.1 UG for Ultra96-V2 has the full pin tables. Look at Tables 7 and 8.
Bryan

#5

Oh I mean do you have any recommendations for an external clk source

#6

We used the IDT Versaclock 6E for all the internal clocks on Ultra96-V2. It is the 5P49V6975A114LTGI on Sheet 7 of the schematics. It is a really versatile device. The programmability made it very easy to configure exactly what we needed in our system. I wrote about that design here:
https://www.element14.com/community/community/designcenter/zedboardcommunity/ultra96/blog/2019/12/02/ultra96-v2-clocking-architecture

You could get the Eval Board and see if you could figure out a way to connect it to one of the expansion connector GC/HDGC pins.
https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p49v6965-evk-evaluation-board-5p49v6965-versaclock-6e

Bryan