CE i2c pull-up spec?


I’m looking for the lowdown on the i2c pull-up specifications for CE boards. The documentation is a bit unclear in this regard;

“It is recommended that a 2K2R pullup is provided on each I2C signal, dependent on any relevant drive/pullup specifications of the SoC.”

I’m trying to understand if this means that as a developer of a mezzanine that uses i2c, I can ASSUME that the i2c will be driven by proper pull-up, or if there is some chance that some board might not.

Do I leave pull-up resistors off of the i2c on the mezzanine? Or do I add them? If I add them, how big?


From my understanding, that means it depends on the SoC pin configuration. If the SoC has I2C pins with internal pull-up, you will need to add (or not) external pull-up so that you get a 2.2Kohm equivalent resistor.

Typically SoCs have software configurable PINs. Configuration is generally described in the device-tree. But even if SoCs have internal ‘generic’ pull-up capabilities, I doubt these pull-ups are well sized for I2C communication.

For example, Dragonboard-410C has its I2C pins free from any pull resistor (bias_disable):

So per my understanding, you must add a 2.2Kohm pull-up resistors (with 1.8v signal) to your mezzanine. I assume 2.2Kohm is propably ok in most scenarios, but if you really want to fine tune your I2C line, I would suggest you to read about this interesting article: http://dsscircuits.com/articles/effects-of-varying-i2c-pull-up-resistors


Funny that you mention the 410c, because it definitely has the pull-up resistors added to its i2c busses already (bottom left of page 5: https://github.com/96boards/documentation/raw/master/consumer/dragonboard410c/hardware-docs/Schematics_DragonBoard.pdf) – and I have 5 i2c devices running successfully on i2c1 without adding any pull-up resistors. Note that I did add pads to my mezzanine for adding pull-up resistors, but have left them unpopulated for now.

What may have been unclear, is that quote was from the CE/SBC design spec, suggesting that the 2.2k resistor be added to the SBC. The mezzanine spec doesn’t mention anything about it.


Ok good point, so this clarify the situation, it’s recommended that CE board provides the pull-up either via SoC internal pull-up, external pull-up, or both. Meaning that mezzanines don’t have to take care of this. Good news, you are going to save two resistors :wink:

on Hikey960 this is external pull-up as well, but 1K resistor (cf schematics).


Well… I can’t say that the savings are really what I’m after (considering that my BOM is running roughly $150), I’m just trying to come up with the optimal configuration. Too much (or too little) pull up can break the bus. I had that problem with a seeed RTC module (grove) that I was playing with a while ago, had to remove the pull-up resistors from it to make it work with the seeed grove sensors mezzanine.

So looks like my best option is to leave the pads present, but unpopulated.


Yes this seems fair in case of adjustment.


That’s pretty much what I would suggest.

An alternative, if you’re designing a mezzanine with an on-board device or level shifter (i.e. we know there is a short wire and low bus capacitance) is to put down the highest value resistor that would work in the absence of a pull up on the base board (meaning design for minimal power, not cleanest transitions). Hopefully you’ll find that this value is likely to be high compared to the 2k2 pull up that may (or may not) be on the base board and the extra pull up won’t break things or increase overall power consumption very much.