Cache specifications of HiKey 960


#1

Dear All

I have been searching online to find the cache specifications of Cortex-A53 and Cortex-A73, primarily the size of the private L1 for data and instructions, shared per cluster unified L2. Additionally, I also want to know if the two clusters share an L3, and if yes, its size.

It will be really helpful if you can point me to data sheets or specs that provide these details, as I am currently unable to find them.

Thanks a lot for your help in advance!


#2

Cortex-A73: 64 KB for the L1 instruction cache and 64 KB for the L1 data cache, 2 MB L2 cache shared by the data and instruction.

Cortex-A53: 32 KB L1 data cache and 32 KB L1 instruction cache, 512 KB L2 cache shared by the data and instruction.

You can find the SoC reference manual at https://www.96boards.org/documentation/consumer/hikey/hikey960/hardware-docs/


#3

Thanks a lot for your prompt reply.

I did browse through this website before, but was not able to track the specs in these documents. It will be great if you can share which document has this information.

I understand that I am asking too much, but would be much obliged if you can help with this.


#4

https://github.com/96boards/documentation/blob/master/consumer/hikey/hikey960/hardware-docs/HiKey960_SoC_Reference_Manual.pdf


#5

Thanks a lot for your help!