@vlvassilev, interesting, could you please add a short description of this project.
We needed an open platform based on the Ultrascale FPGA family. We used Ultra96 and designed a mezzanine. We decided to put out that as a product itself and open the design (KiCad).
You get eth0-eth5 1Gb SFP+ interfaces in Ultra96 petalinx with full FPGA dataplane programability. We have added a dumb traffic generator that generates 64 byte ethernet frames with minimum gap implementation in Verilog as an example IP module. There is also a simple gmii_mux to change the source of the egress traffic between the DMA traffic generated by the Zynq processor and the traffic generated by the traffic generator in PL.
To get the hardware fit vertically in a 19 inch rack 1U and still have space for 2 additional mezzanine boards (glue logic to the SFP+ and GPS with timing synchronization) we have translated the extension interface for “secondary” mezzanine boards “behind” the Ultra96 connectors.
The information in the kickstarter campaing has links to the github repositories (here is a copy):
The design files including board and mechanics are published under the TAPR Open Hardware License. Link to the repository https://github.com/lightside-instruments/spark
We have published opensource reference FPGA design with petalinux support https://github.com/lightside-instruments/network-interconnect-tester-cores
You can also buy the v1 version of the board from our website https://lightside-instruments.com/index.php/product/spark-v1-6-sfpplus-mezzanine-expansion/