Any configuration that I need to enable the pcm lines on the low-speed expansion header?

Hey guys,

I am trying to enable the i2s lines that are exposed on the low-speed expansion header on the hikey.
I tweaked the i2s driver and enabled the s3 intereface clock by writing into a register and did few configurations related to the s3 i2s. By doing that it should generate the clock (BCLK and LRCLK).
I am not bothering about the data in and data out currently.

The thing that I want to know is, I am not getting any signals from the low-speed expansion header.
What I need to do to enable the low-speed exapsion header lines.

If I can enable I may get the clock.

Current i2s settings in the dtsi

		i2s0: hi6210_i2s {
			compatible = "hisilicon,hi6210-i2s";
			reg = <0x0 0xf7118000 0x0 0x8000>, /* i2s unit */
			      <0x0 0xf7030000 0x0 0x400>,  /* syscon */
			      <0x0 0xf7032000 0x0 0x400>;  /* pmctrl */
			interrupts = <0 123 0x4>; /* 155 "DigACodec_intr" - 32 */
			pinctrl-names = "default";
			pinctrl-0 = <&bt_pmx_func &bt_cfg_func>;
			clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
				 <&sys_ctrl HI6220_BBPPLL0_DIV>;
			clock-names = "dacodec", "i2s-base";
			dmas = <&dma0 15 &dma0 14>;
	                dma-names = "rx", "tx";
		};

The thing that I am doubting here is about the pinctrl-0 = <&bt_pmx_func &bt_cfg_func>;
What I need to change to enable the lines on the low-speed expansion header.

Or Any suggestions on debugging this can help alot.

Any suggestions and tips welcome

Hi there,

I checked the design for LS expansion port: https://github.com/96boards/documentation/blob/master/ConsumerEdition/HiKey/AdditionalDocs/HiKey_User_Guide_CircuitCo.pdf

In Hikey CircuitCo version, you could see the LS expansion port uses I2S bus which connects with Hi6220’s 4 pins:
MODEM_PCM_XFS
MODEM_PCM_XCLK
MODEM_PCM_DO
MODEM_PCM_DI

So I think the PINMUX should be defined as below:

diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
index 0916e84..824daf6 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
@@ -230,6 +230,15 @@
                                        0x1ac  MUX_M1   /* SPI0_CLK     (IOMG107) */
                                >;
                        };
+
+                       modem_pcm_pmx_func: modem_pcm_pmx_func {
+                               pinctrl-single,pins = <
+                                       0x198  MUX_M3   /* MODEM_PCM_XCLK      (IOMG102) */
+                                       0x19c  MUX_M3   /* MODEM_PCM_XFS       (IOMG103) */
+                                       0x1d0  MUX_M3   /* MODEM_PCM_DI        (IOMG116) */
+                                       0x1d4  MUX_M3   /* MODEM_PCM_DO        (IOMG117) */
+                               >;
+                       };
                };
 
                pmx1: pinmux@f7010800 {
@@ -595,6 +604,18 @@
                                pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
                        };
 
+                       modem_pwm_cfg_func: modem_pwm_cfg_func {
+                               pinctrl-single,pins = <
+                                       0x1a8  0x0      /* MODEM_PCM_XCLK      (IOCFG106) */
+                                       0x1ac  0x0      /* MODEM_PCM_XFS       (IOCFG107) */
+                                       0x1e0  0x0      /* MODEM_PCM_DI        (IOCFG120) */
+                                       0x1e4  0x0      /* MODEM_PCM_DO        (IOCFG121) */
+                               >;
+                               pinctrl-single,bias-pulldown  = <PULL_DIS  PULL_DOWN PULL_DIS  PULL_DOWN>;
+                               pinctrl-single,bias-pullup    = <PULL_DIS  PULL_UP   PULL_DIS  PULL_UP>;
+                               pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+                       };
+
                        uart5_cfg_func: uart5_cfg_func {
                                pinctrl-single,pins = <
                                        0x1d8  0x0      /* UART4_RXD    (IOCFG118) */

I think the clock also need to use specific flow to enable:

/* Release reset */
If SC_PERIPH_RSTSTAT2 (0xF7030328).bit4 != 0
SC_PERIPH_RSTDIS2 (0xF7030324).bit4 = 0x1

/* Enable BBP PLL */
PMCTRL_BBPPLLALIAS.bit0 = 1, I have not found related info for this register. Let me check furthermore internally.

/* Enable clock before divider */
SC_PERIPH_CLKEN12 (0xF7030270).bit9 = 1

/* Enable codec clock */
SC_PERIPH_CLKEN1 (0xF7030210).bit5 = 1

Hey there,

Thank you for the reply :slight_smile: .

I will try those now.

This may be a stupid question but how did you get the pin numbers

0x198  MUX_M3   /* MODEM_PCM_XCLK      (IOMG102) */
0x19c  MUX_M3   /* MODEM_PCM_XFS       (IOMG103) */
0x1d0  MUX_M3   /* MODEM_PCM_DI        (IOMG116) */
0x1d4  MUX_M3   /* MODEM_PCM_DO 

0x1a8  0x0      /* MODEM_PCM_XCLK      (IOCFG106) */
0x1ac  0x0      /* MODEM_PCM_XFS       (IOCFG107) */
0x1e0  0x0      /* MODEM_PCM_DI        (IOCFG120) */
0x1e4  0x0      /* MODEM_PCM_DO

I tried to get the pin number but I didn’t find anywhere :confused:.

Any documentation about the pin muxing stuff?

The missed register PMCTRL_BBPPLLALIAS address is: 0xF7032048.

Yay, Getting some(BCLK) clock :slight_smile: :smiley:

Now I need to work for the other stuff like data in and data out and lrclk.

Thank you @leo-yan

Great to hear Leo has got you moving forward.

Let’s keep the discussion going here… I’m planning to close some of the other cross-posted Hikey I2S threads now (aren’t there four now?).

Yaa, Its better to close them.

I post any update that I had in here.

Thank you guys for the wonderful support :slight_smile:

Hi guys,

Do you have any idea on which fifo I need to use for sending the data through those lines on the header?

Currently, the driver is for s2 and they are using ST DL Fifos etc.

Is there any document that I can refer to know about those settings or something that help me to go further?

I tried few experiment changes but nothing positive.

Any suggestions can be so much helpful to me.