The hikey960 schematics shows that I2S0 shares CPU pins with UART7.
Is Hisilicon planning to provide DTS mux/cfg settings for UART7 ?
I thought that i2s0 was routed to the i2s pins on the low speed header? Or do you mean using the i2s pins as uart?
I mean using I2S0 LS pins as third UART.