Use WUXGA LCD panel on DragonBoard 410C


#1

Hi,

I have followed DSI Porting Guide and used the excel file to generate the dtsi file. The boot log shows
mdss_dsi_fifo_status: status=55551000
mdss_dsi_timeout_status: status=1

Refer to p.3928-3930, the hardware register description, the FIFO of 4 lanes overflow (44440000) and empty (11110000), and FIFO for LP data on Lane 0 is empty (00001000). I have no idea what is going wrong. Would anyone give me some advice?

Thanks and regards,
raym


#2

Hi,

After DSI_SW_SEL_APQ is set to high, the problem is fixed.


#3

Hi raym,

Did you manage to turn on your WUXGA LCD panel? Could you, please, give some more details on the model? What is this LCD panel name (p/n), dot resolution, color depth, frame frequency? I am looking for any info on the successful connection of FullHD (1920x1080) or WUXGA (1920x1200), 24bpp, 60fps MIPI-DSI panel to DB410C (through HS connector) but can’t find anything.

Thanks,
Alex


#4

Hi Alex,

It’s B101UAN01.7. You may google to get the specification.


#5

Hi,

I encounter another DSI error that
[ 21.572965] mdss_dsi_ack_err_status: status=1000002
[ 21.576807] mdss_dsi_timeout_status: status=1

The hrd document says it’s “SoT Sync Error detected by the DSI display module”. Check the MIPI spec,
SoT Sync Error
If the SoT Leader sequence is corrupted in a way that proper synchronization cannot be expected, a SoT
Sync Error is indicated

Is it an error detected by the SoC itself or received from the LCD panel? What are the possible causes?

Thanks a lot in advance!


#6

Hi Raym,
Check your porch configurations, try not to set them too small. I assume your mipi bus is working since you can get “SoT Sync Error” from DSI display module.


#7

Hi mipiminer,

Thanks for your advice. The LCD spec states the typical values that
Horizontal Section, Period=2040, Active=1920, Blanking=120
Vertical Section, Period=1212, Active=1200, Blanking=12

I have tried different values like
qcom,mdss-dsi-h-front-porch = <24>;
qcom,mdss-dsi-h-back-porch = <36>;
qcom,mdss-dsi-h-pulse-width = <60>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <8>;
qcom,mdss-dsi-v-front-porch = <2>;
qcom,mdss-dsi-v-pulse-width = <2>;
or
qcom,mdss-dsi-h-front-porch = <36>;
qcom,mdss-dsi-h-back-porch = <72>;
qcom,mdss-dsi-h-pulse-width = <12>;
qcom,mdss-dsi-h-sync-skew = <0>;
qcom,mdss-dsi-v-back-porch = <8>;
qcom,mdss-dsi-v-front-porch = <2>;
qcom,mdss-dsi-v-pulse-width = <2>;
But it still does not work. Sometimes I get other messages
[ 72.636581] mdss_dsi_fifo_status: status=55551000
[ 72.712926] mdss_dsi_bta_status_check: DSI BTA error: 0
[ 72.717115] mdss_dsi_bta_status_check: BTA done with ret: 0
[ 72.732981] mdss_dsi_ctl_phy_reset: lane status, ctrl = 0x1f0e
[ 72.737780] mdss_dsi_ctl_phy_reset: lane status = 0x1f1f
[ 72.764910] mdss_report_panel_dead: Panel has gone bad, sending uevent - PANEL_ALIVE=0

Do you have any more suggestions?

Thanks a lot!


#8

Hi Raym,
First, you can read data from your panel to make sure panel boots in correct power on sequence.
===read command in console===
cd /sys/kernel/debug/mdp
echo 09 4 > panel_off
cat panel_reg //check if you can read data from your panel.

Then, you can run below command to make sure your clk is expected.

su
cat /sys/kernel/debug/clk/gcc_mdss_byte0_clk/rate
cat /sys/kernel/debug/clk/pixel_clk_src_8916/rate
cat /sys/kernel/debug/clk/mdp_clk_src/rate
cat /sys/kernel/debug/mdss_panel/dsi0/*

If these numbers are expected, you might need to check the mipi lane signals by scope.

BRs,
Henry


#9

Hello,

I am interested in same display, have you able to configure successfully?

Thanks


#10

Hi,

Yes, it can work.


#11

Hi
Can you explain how you configure the lcd?
Thanks