Ultra96: DDR4 port is unavailable in vivado block diagram

I’m creating a custom IP using RTL which needs to read and write to memory. I would like to do burst reads and writes via AXI stream. However, when I add a ZYNQ Ultrascale+ IP to the block diagram and run block automation, I get the following:

However, in Zedboards with Z7000 SOCs, the DDR4 is readily available as a port in the ZYNQ IP itself.

How can I get access to the DDR port? Or, where can I connect an AXI DMA to interface the DDR4 to my custom IP?

Thank you. I would greatly appreciate any help.