Thanks Todortomov for the explanation. I’ll try some various values of settle-cnt as you suggest.
kimbo
我想知道是否能用中文发帖,我在网站里能否找到中文内容的帖子。
Hi Todortomov,
This reply really hits on my puzlle, how about the supported csiphy0_timer_clk at DB410?
I am trying working out a RAW sensor, but with a 250MHz clock lane, will it work? Can you please advise me how should I configure my ‘core clock’?
Thanks and regards,
Yunfei