Make two components cohesists in spi bus

Hello @doitright, Hello @all,

I hope you’re going well.

I’m working with i.MX6 SOM , and I have a question about how to make two components coexist in Devicetree (SPI bus).
I’ve two components declared in the ecspi3 bus, in the Devicetree. A NOR flash memory (mx25u6435f) and a quad uart (max14830)
I want them to initialize correctly together on the bus to be able to access it.
Both components are located on the i.MX6 ecspi3 bus. The NOR flash memory is on chip select 1 and the quad uart is on chip select 0.

Here is the Devicetree of the concerned spi bus:


&ecspi3 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 25 0>, <&gpio4 24 0>;
num-cs = <2>;
pinctrl-names = “default”;
pinctrl-0 = <&pinctrl_ecspi3_1>;
status = “okay”;

    quad_uart: spimax14830@0 {
        
        compatible = "maxim,max14830";
        spi-max-frequency = <100000>;
        reg = <0>;
        clocks = <&max14830_clock>;
        clock-names = "xtal";

        gpio-controller;
        #gpio-cells = <2>;
        interrupt-controller;
        #interrupt-cells = <2>;

        interrupt-parent = <&gpio4>;
        interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
        
        status="okay";
    };
    module_flash2: spinor@1 {
            
           #address-cells = <1>;
           #size-cells = <1>;
           compatible = "spansion,m25p80","jedec,spi-nor";
           spi-max-frequency = <100000>;
           reg = <1>;
           partition@0 {
                   label = "thx_boarddata";
                   reg = <0x0 0x800000>;
           };
   };

};

Here is other environment nodes:


clocks{
max14830_clock: clkmax14830{
compatible = “fixed-clock”;
#clock-cells = <0>;
clock-frequency = <3686400>;
};
};

ecspi3 {
pinctrl_ecspi3_1: ecspi3grp-1 {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x30b1 /* SPI3_SS0n /
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x30b1 /
SPI3_SS1n */
>;
};
};

With these Devicetree parameters, I observe 3 different cases in kernel log after system booting with the command: “dmesg |grep spi”

case 1: if only the quad uart is physically wired, it is recognized and initialized on chip select 0:

root@pc:~# dmesg |grep spi

[ 1.964927] spi2.0: ttyMAX0 at I/O 0x0 (irq = 181, base_baud = 2764800) is a MAX14830
[ 1.975222] spi2.0: ttyMAX1 at I/O 0x20 (irq = 181, base_baud = 2764800) is a MAX14830
[ 1.985565] spi2.0: ttyMAX2 at I/O 0x40 (irq = 181, base_baud = 2764800) is a MAX14830
[ 1.995902] spi2.0: ttyMAX3 at I/O 0x60 (irq = 181, base_baud = 2764800) is a MAX14830
[ 2.006738] m25p80 spi2.1: unrecognized JEDEC id bytes: 00, 00, 00
[ 2.012968] spi_imx 2010000.ecspi: probed

That’s the expected behaviour because only quad uart is wired to the spi bus.

case 2: if the quad uart is physically unwired and only the NOR flash memory is wired, then it is recognized and initialized on chip select 1:

root@pc:~# dmesg |grep spi

[ 1.951279] max310x spi2.0: MAX14830 ID 0x00 does not match
[ 1.958397] m25p80 spi2.1: found mx25u6435f, expected m25p80
[ 1.964095] m25p80 spi2.1: mx25u6435f (8192 Kbytes)
[ 1.968994] 1 fixed-partitions partitions found on MTD device spi2.1
[ 1.975373] Creating 1 MTD partitions on “spi2.1”:
[ 1.986638] spi_imx 2010000.ecspi: probed

That’s the expected behaviour because only NOR flash memory is wired to the spi bus.

case 3: if the 2 components (NOR flash memory and quad uart) are physically wired to the ecspi3 bus, only the quad uart is recognized and initialized on chip select 0:

root@pc:~# dmesg |grep spi

[ 1.964927] spi2.0: ttyMAX0 at I/O 0x0 (irq = 181, base_baud = 2764800) is a MAX14830
[ 1.975222] spi2.0: ttyMAX1 at I/O 0x20 (irq = 181, base_baud = 2764800) is a MAX14830
[ 1.985565] spi2.0: ttyMAX2 at I/O 0x40 (irq = 181, base_baud = 2764800) is a MAX14830
[ 1.995902] spi2.0: ttyMAX3 at I/O 0x60 (irq = 181, base_baud = 2764800) is a MAX14830
[ 2.006738] m25p80 spi2.1: unrecognized JEDEC id bytes: 00, 00, 00
[ 2.012968] spi_imx 2010000.ecspi: probed

That’s not normal. The behaviour expected was the correct initialisation of both components because both are wired on spi bus.

As in the first 2 cases, the components are initialized on the chip select which corresponds to them, there is surely something in the Devicetree which does not specify that there are two components to use. But I don’t know what’s wrong in the Devicetree.

If you have answers, thank you in advance.

Best reguards, Anthony.