LK Continuous splash screen

Hi everyone,

We have a splash screen displayed during LK, then psplash is started during boot.
However the delay between the LK splash screen and psplash is quite long.
Indeed, our MIPI display is first initialized in the bootloader, then it’s reinitialized in the kernel.
We already tried to add a kernel logo, but it wouldn’t display anything as the second MIPI initialization takes a lot of time in the kernel (display working only at 16/17s and psplash starts immediately after). It takes about 7 seconds to send 95 init MIPI commands to the display, which is really slow…

So we would like to have a continuous splash screen from LK to kernel by keeping the display initialized in LK to the kernel (skipping the second initialization). We would like to have the same behavior as this config in u-boot: CONFIG_FB_PRE_INIT_FB - NXP Community

By default, when we leave the bootloader the display should not be turn off, as continuous splash screen is enabled. But, the screen gets blanked once in the kernel.
How could we configure our display in the kernel to keep the LK splash screen displayed?
We are using the linux-linaro-qcomlt kernel version 4.14 and LK bootloader.
We already tried to add the qcom,cont-splash-enabled attribute to the device-tree, but it’s not working.

Do you have any ideas on how we could implement it?

Thanks.

Hi,
We tried to adapt and apply following patches without success for now: https://marc.info/?l=dri-devel&m=149979722606563&w=2
The device is stucked at the end of the bootloader (“Jumping to kernel via monitor”).
I’m open to any other ideas.
Thanks.

well it is possible but you need to:

  • be sure that the memory used by splashscreen is no re-used by the kernel, so that the media subsystem (mdss) hw can continue reading the splash data. That can be done by adding the corresponding memory node (with no-map) under reserved-memory {} in the devicetree.
  • You need to be sure that mdss clocks will not be automatically disabled by the kernel at boot time (since they are initially no considered used by Linux), the simpler way is to pass clk_ignore_unused parameter to kernel boot command.

At this point, and if you disable the mdss driver, splash should be preserved. Then you’ll need to customize the mdss driver:

  • You will probably to need to workaround mdss init function, to discard mdss reset/initializion (e.g. in mdp5_hw_init) at least until new userspace takes over an try to submit new frames (e.g. mdp5_prepare_commit)… so a bunch of tiny changes…

Hi Loic,

Thanks for your help.

We defined our splash reserved-memory node in our device-tree and we added clk_ignore_unused parameter to kernel boot command.
With mdss driver disabled, the splash screen isn’t preserved when booting into the kernel.

What else could prevent the splash screen to be preserved?

maybe try also adding pd_ignore_unused, to prevent display power domain to be powered off. You may want to check also if you depend on some regulator in the dts, and mark them as regulator-always-on for testing purpose.

We added pd_ignore_unused and marked the three depending regulators in the device tree as always-on, but the screen still gets blanked once in the kernel (backlight is on). We’ll try to find what else could turn off the splash screen…

You might be able to use a combination of initcall_debug debug boot_delay=100 (boot_delay required CONFIG_BOOT_PRINTK_DELAY to be set) to both instrument the boot and slow things down enough for you to figure out what driver is coming up when the splash turns off.

In short if you have local echo turned on in whatever tool you use the observe the serial console then you can watch the slow motion boot and stab the Enter key when the splash screen goes away then you have a marker in the trace that shows roughly when the splash screen was dropped. It is likely that somewhere in the last second is a clue about what driver or bus was registered just before things break.

Look for anything that sounds like it could be related to display or smmu.

We noticed that we have mdss gdsc, smmu_mdp_ahb_clk and smmu_mdp_axi_clk turned off at the probe of mmcc-msm8996 driver. So we removed turning off those clocks. The splash screen is now preserved until smmu driver probe. Then, the som is crashing.

Crash Log:
[ 10.548980] calling arm_smmu_driver_init+0x0/0x24 @ 1
[ 10.555523] arm-smmu da0000.arm,smmu: probing hardware configuration…
[ 10.560003] arm-smmu da0000.arm,smmu: SMMUv2 with:
[ 10.566524] arm-smmu da0000.arm,smmu: stage 1 translation
[ 10.571353] arm-smmu da0000.arm,smmu: address translation ops
[ 10.576807] arm-smmu da0000.arm,smmu: non-coherent table walk
[ 10.582641] arm-smmu da0000.arm,smmu: (IDR0.CTTW overridden by FW configuration)
[ 10.588445] arm-smmu da0000.arm,smmu: stream matching with 4 register groups
[ 10.596056] arm-smmu da0000.arm,smmu: 2 context banks (0 stage-2 only)
[ 10.603142] arm-smmu da0000.arm,smmu: Supported page sizes: 0x63315000
[ 10.609571] arm-smmu da0000.arm,smmu: Stage-1: 32-bit VA → 36-bit IPA
[ 10.617842] arm-smmu d00000.arm,smmu: probing hardware configuration…
[ 10.622751] arm-smmu d00000.arm,smmu: SMMUv2 with:
[ 10.629364] arm-smmu d00000.arm,smmu: stage 1 translation
[ 10.634186] arm-smmu d00000.arm,smmu: address translation ops
[ 10.639653] arm-smmu d00000.arm,smmu: non-coherent table walk
[ 10.645471] arm-smmu d00000.arm,smmu: (IDR0.CTTW overridden by FW configuration)
[ 10.651290] arm-smmu d00000.arm,smmu: stream matching with 2 register groups
[ 10.658865] arm-smmu d00000.arm,smmu: 2 context banks (0 stage-2 only)
[ 10.665996] arm-smmu d00000.arm,smmu: Supported page sizes: 0x63315000
[ 10.672375] arm-smmu d00000.arm,smmu: Stage-1: 32-bit VA → 36-bit IPA
[ 10.681213] arm-smmu 1600000.arm,smmu-lpass_q6: probing hardware configuration…
[ 10.685701] arm-smmu 1600000.arm,smmu-lpass_q6: SMMUv2 with:
[ 10.693331] arm-smmu 1600000.arm,smmu-lpass_q6: stage 1 translation
[ 10.698936] arm-smmu 1600000.arm,smmu-lpass_q6: address translation ops
[ 10.705294] arm-smmu 1600000.arm,smmu-lpass_q6: non-coherent table walk
[ 10.711957] arm-smmu 1600000.arm,smmu-lpass_q6: (IDR0.CTTW overridden by FW configuration)
[ 10.718659] arm-smmu 1600000.arm,smmu-lpass_q6: stream matching with 15 register groups
[ 10.726756] arm-smmu 1600000.arm,smmu-lpass_q6: 12 context banks (0 stage-2 only)
[ 10.735094] arm-smmu 1600000.arm,smmu-lpass_q6: Supported page sizes: 0x63315000
[ 10.742429] arm-smmu 1600000.arm,smmu-lpass_q6: Stage-1: 36-bit VA → 36-bit IPA
[ 10.754720] arm-smmu d40000.arm,smmu-venus: probing hardware configuration…
[ 10.757541] arm-smmu d40000.arm,smmu-venus: SMMUv2 with:
[ 10.764689] arm-smmu d40000.arm,smmu-venus: stage 1 translation
[ 10.769943] arm-smmu d40000.arm,smmu-venus: address translation ops

Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00331-M8996LZB-1
S - IMAGE_VARIANT_STRING=M8996LAB
S - OEM_IMAGE_VERSION_STRING=jenkins
S - Boot Interface: UFS
S - Secure Boot: Off
S - Boot Config @ 0x00076044 = 0x000001c9
S - JTAG ID @ 0x000760f4 = 0x100640e1
S - OEM ID @ 0x000760f8 = 0x00000000
S - Serial Number @ 0x00074138 = 0x8bd89cf1
S - OEM Config Row 0 @ 0x00074188 = 0x0000000000000000
S - OEM Config Row 1 @ 0x00074190 = 0x0000000000000000
S - Feature Config Row 0 @ 0x000741a0 = 0x0050000010000100
S - Feature Config Row 1 @ 0x000741a8 = 0x00fff00001ffffff
S - Core 0 Frequency, 1228 MHz
B - 0 - PBL, Start
B - 10411 - bootable_media_detect_entry, Start
B - 47073 - bootable_media_detect_success, Start
B - 47074 - elf_loader_entry, Start
B - 48091 - auth_hash_seg_entry, Start
B - 48192 - auth_hash_seg_exit, Start
B - 80089 - elf_segs_hash_verify_entry, Start
B - 82580 - PBL, End
B - 84576 - SBL1, Start
B - 181078 - usb: hs_phy_nondrive_start
B - 181414 - usb: PLL lock success - 0x3
B - 184403 - usb: hs_phy_nondrive_finish
B - 188551 - boot_flash_init, Start
D - 30 - boot_flash_init, Delta
B - 195627 - sbl1_ddr_set_default_params, Start
D - 0 - sbl1_ddr_set_default_params, Delta
B - 203618 - boot_config_data_table_init, Start
D - 95068 - boot_config_data_table_init, Delta - (60 Bytes)
B - 303231 - CDT Version:3,Platform ID:10,Major ID:1,Minor ID:0,Subtype:28
B - 307989 - Image Load, Start
D - 22265 - PMIC Image Loaded, Delta - (37464 Bytes)
B - 330254 - pm_device_init, Start
B - 336018 - PON REASON:PM0:0x20020 PM1:0x20020
B - 372496 - PM_SET_VAL:Skip
D - 40077 - pm_device_init, Delta
B - 374418 - pm_driver_init, Start
D - 2897 - pm_driver_init, Delta
B - 381006 - pm_sbl_chg_init, Start
D - 91 - pm_sbl_chg_init, Delta
B - 387777 - vsense_init, Start
D - 0 - vsense_init, Delta
B - 395707 - Pre_DDR_clock_init, Start
D - 396 - Pre_DDR_clock_init, Delta
B - 401380 - ddr_initialize_device, Start
B - 405070 - 8996 Pro v1.x detected, Max frequency = 1.8 GHz
B - 412634 - ddr_initialize_device, Delta
B - 415044 - Basic DDR tests done
B - 1977833 - clock_init, Start
D - 244 - clock_init, Delta
B - 1979846 - Image Load, Start
D - 6679 - QSEE Dev Config Image Loaded, Delta - (48160 Bytes)
B - 1986770 - Image Load, Start
D - 5215 - APDP Image Loaded, Delta - (0 Bytes)
B - 2013823 - usb: fedl, vbus_low
B - 2013884 - Image Load, Start
D - 10706 - XBLRamDump Image Loaded, Delta - (342878 Bytes)
B - 2079185 - usb: init start
B - 2080832 - usb: radagast_qusb2phy_tune1_5
B - 2081289 - usb: PLL lock success , 0x2

Hmmnnn… that’s a nice illustration of why continuous splash is getting much harder on modern chips :wink: .

I don’t have very much in the way of practical advice on how to fix it. I suspect that during the smmu init the DMA configured by the bootloader to keep the display up to date stops working (initializing the smmu changes the IOVAs that the DMA must use).

You could try hunting down how smmu init problems were solved on the sdm845 laptops. I’m not familiar with how the smmu/display subsystem is managed on this devices but the EFI framebuffer on these laptops is essentially the same as a continuous splash screen (only difference being that the kernel deliberately changes the content on display as it boots).

So, maybe try to disable CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT, or using arm-smmu.disable_bypass=0 parameter, this should prevent disabling IOMMU (bypass mode) at init. But for this, the IOMMU should be already configured in bypass mode by the bootloader, don’t know if it is the case here.

Alternatively, try to move ‘qcom,smmu-v2’ compatible string from drivers/iommu/arm/arm-smmu/arm-smmu.c to drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c, but it’s purely speculative… this specific driver is looking for iommu client, and if it’s the MDSS (display subsystem), it forces the IOMMU to identity/bypass mapping, so that the display pipeline can continue polling the framebuffer area.

We added arm-smmu.disable_bypass=0 parameter but the som is still crashing at smmu probing.

We are based on linux linaro kernel 4.14 not android (working/qualcomm/kernel.git - Qualcomm Landing Team kernel), so we don’t have drivers/iommu/arm/arm-smmu/arm-smmu.c and drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c but only drivers/iommu/arm-smmu.c.

So instead of maintaining the bootloader splash, we are trying to speed up the panel driver probe. The panel module and DRM_MSM module were loaded as external modules, so we tried to load them as builtin modules. However now, the soc is failing to boot:
[ 13.949474] deferred probe b40000.arm,smmu returned after 59940 usecs
[ 13.955557] deferred probe b00000.gpu @ 1411
[ 13.962512] iommu: Adding device b00000.gpu to group 1
[ 13.966575] adreno b00000.gpu: Linked as a consumer to b40000.arm,smmu
[ 13.971798] [drm:msm_mdss_init]
[ 13.978013] msm 900000.mdss: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 13.981405] msm 900000.mdss: 900000.mdss supply vdd not found, using dummy regulator
[ 13.989913] [drm:mdp5_bind]
[ 13.997841] msm_mdp 901000.mdp: Using legacy clk name binding. Use “bus” instead of “bus_clk”
[ 14.000626] msm_mdp 901000.mdp: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 14.009074] msm_mdp 901000.mdp: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 14.018043] msm_mdp 901000.mdp: Using legacy clk name binding. Use “vsync” instead of “vsync_clk”
[ 14.026911] [drm:get_clk] skipping lut
[ 14.035784] [drm:msm_runtime_resume]
[ 14.039399] [drm:msm_mdss_enable]
[ 14.043159] [drm:mdp5_runtime_resume]
[ 14.046415] [drm:mdp5_enable]
[ 14.050176] [drm:mdp5_runtime_suspend]
[ 14.053199] [drm:mdp5_disable]
[ 14.056948] msm_mdp 901000.mdp: MDP5 version v1.7
[ 14.060069] [drm:mdp5_cfg_init] MDP5: msm8x96 hw config selected
[ 14.064934] [drm:mdp5_ctlm_init] Pool of 5 CTLs created.
[ 14.071015] msm 900000.mdss: bound 901000.mdp (ops mdp5_ops)
[ 14.076298] [drm:dsi_bind]
[ 14.081931] [drm:dsi_bind] dsi probed=ffff8000f8a1e198
[ 14.084471] no valid remote node
[ 14.089691] valid remote: /soc/mdss@900000/dsi@994000/panel@0 for node /soc/mdss@900000/dsi@994000/ports/port@1/endpoint@0
[ 14.093184] [drm:msm_runtime_suspend]
[ 14.103894] [drm:msm_mdss_disable]
[ 14.793121] msm_dsi 994000.dsi: 994000.dsi supply gdsc not found, using dummy regulator
[ 14.793214] [drm:msm_runtime_resume]
[ 14.799922] [drm:msm_mdss_enable]
[ 14.803748] [drm:msm_dsi_host_init] dsi_get_config: Version 3:10040001
[ 14.803748]
[ 14.807093] [drm:msm_runtime_suspend]
[ 14.814946] [drm:msm_mdss_disable]
[ 14.818830] msm_dsi 994000.dsi: Using legacy clk name binding. Use “mdp_core” instead of “mdp_core_clk”
[ 14.822164] msm_dsi 994000.dsi: Using legacy clk name binding. Use “mmagic_iface” instead of “mmagic_iface_clk”
[ 14.831896] msm_dsi 994000.dsi: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 14.842058] msm_dsi 994000.dsi: Using legacy clk name binding. Use “bus” instead of “bus_clk”
[ 14.850835] msm_dsi 994000.dsi: Using legacy clk name binding. Use “byte” instead of “byte_clk”
[ 14.859434] msm_dsi 994000.dsi: Using legacy clk name binding. Use “pixel” instead of “pixel_clk”
[ 14.868380] msm_dsi 994000.dsi: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 14.877103] [drm:msm_dsi_host_init] Dsi Host 0 initialized
[ 14.886134] [drm:msm_runtime_resume]
[ 14.891327] [drm:msm_mdss_enable]
[ 14.895067] [drm:msm_dsi_runtime_resume] id=0
[ 14.898419] Probe hx8279d
[ 14.902781] Add panel hx8279d
[ 14.905486] [drm:dsi_host_attach] id=0
[ 14.908364] msm 900000.mdss: bound 994000.dsi (ops dsi_ops)
[ 14.912000] [drm:msm_hdmi_bind] failed to get gpio: qcom,hdmi-tx-ddc-clk (-2)
[ 14.917458] [drm:msm_hdmi_bind] failed to get gpio: qcom,hdmi-tx-ddc-data (-2)
[ 14.924753] [drm:msm_hdmi_bind] failed to get gpio: qcom,hdmi-tx-hpd (-2)
[ 14.931869] [drm:msm_hdmi_bind] failed to get gpio: qcom,hdmi-tx-mux-en (-2)
[ 14.938728] [drm:msm_hdmi_bind] failed to get gpio: qcom,hdmi-tx-mux-sel (-2)
[ 14.945840] [drm:msm_hdmi_bind] failed to get gpio: qcom,hdmi-tx-mux-lpm (-2)
[ 14.953054] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 14.960021] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 14.969211] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “mdp_core” instead of “mdp_core_clk”
[ 14.978607] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “extp” instead of “extp_clk”
[ 14.988492] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “alt_iface” instead of “alt_iface_clk”
[ 14.997751] [drm:msm_dsi_runtime_suspend]

Boot with DRM_MSM as external module:
[ 17.768308] [drm:msm_dsi_host_init [msm]] Dsi Host 0 initialized
[ 17.777296] [drm:msm_runtime_resume [msm]]
[ 17.783039] [drm:msm_mdss_enable [msm]]
[ 17.786966] [drm:msm_dsi_runtime_resume [msm]] id=0
[ 17.791176] [drm:msm_dsi_runtime_suspend [msm]]
[ 17.795758] [drm:msm_runtime_suspend [msm]]
[ 17.798115] msm_dsi_manager_register: failed to register mipi dsi host for DSI 0
[ 17.798320] [drm:msm_dsi_host_destroy [msm]]
[ 17.798620] msm 900000.mdss: failed to bind 994000.dsi (ops dsi_ops [msm]): -517
[ 17.816503] [drm:msm_mdss_disable [msm]]
[ 17.824110] msm 900000.mdss: master bind failed: -517
[ 17.828097] initcall msm_drm_register+0x0/0x80 [msm] returned 0 after 994616 usecs
[ 17.834487] [drm:msm_mdss_init [msm]]
[ 17.834603] msm 900000.mdss: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 17.834660] msm 900000.mdss: 900000.mdss supply vdd not found, using dummy regulator
[ 17.834901] [drm:mdp5_bind [msm]]
[0m.
[ 17.834960] msm_mdp 901000.mdp: Using legacy clk name binding. Use “bus” instead of “bus_clk”
[ 17.834972] msm_mdp 901000.mdp: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 17.835000] msm_mdp 901000.mdp: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 17.835041] msm_mdp 901000.mdp: Using legacy clk name binding. Use “vsync” instead of “vsync_clk”
[ 17.835097] [drm:get_clk [msm]] skipping lut
[ 17.835175] [drm:msm_runtime_resume [msm]]
[ 17.835227] [drm:msm_mdss_enable [msm]]
[ 17.835304] [drm:mdp5_runtime_resume [msm]]
[ 17.835356] [drm:mdp5_enable [msm]]
[ 17.835423] [drm:mdp5_runtime_suspend [msm]]
[ 17.835475] [drm:mdp5_disable [msm]]
[ 17.835491] msm_mdp 901000.mdp: MDP5 version v1.7
[ 17.835546] [drm:mdp5_cfg_init [msm]] MDP5: msm8x96 hw config selected
[ 17.835608] [drm:mdp5_ctlm_init [msm]] Pool of 5 CTLs created.

[ 19.458492] [drm:msm_mdss_init [msm]]
[ 19.459009] msm 900000.mdss: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 19.459067] msm 900000.mdss: 900000.mdss supply vdd not found, using dummy regulator
[ 19.459387] [drm:mdp5_bind [msm]]
[ 19.459482] msm_mdp 901000.mdp: Using legacy clk name binding. Use “bus” instead of “bus_clk”
[ 19.459495] msm_mdp 901000.mdp: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 19.459526] msm_mdp 901000.mdp: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 19.459566] msm_mdp 901000.mdp: Using legacy clk name binding. Use “vsync” instead of “vsync_clk”
[ 19.459631] [drm:get_clk [msm]] skipping lut
[ 19.459729] [drm:mdp5_runtime_resume [msm]]
[ 19.459775] [drm:mdp5_enable [msm]]
[ 19.459830] [drm:mdp5_runtime_suspend [msm]]
[ 19.459880] [drm:mdp5_disable [msm]]
[ 19.459891] msm_mdp 901000.mdp: MDP5 version v1.7
[ 19.459944] [drm:mdp5_cfg_init [msm]] MDP5: msm8x96 hw config selected
[ 19.460048] [drm:mdp5_ctlm_init [msm]] Pool of 5 CTLs created.
[ 19.460105] msm 900000.mdss: bound 901000.mdp (ops mdp5_ops [msm])
[ 19.460153] [drm:dsi_bind [msm]]
[ 19.460201] [drm:dsi_bind [msm]] dsi probed=ffff8000f1520e18
[ 19.460217] no valid remote node
[ 19.460306] valid remote: /soc/mdss@900000/dsi@994000/panel@0 for node /soc/mdss@900000/dsi@994000/ports/port@1/endpoint@0
[ 19.461766] initcall qcom_venus_dec_driver_init+0x0/0x1000 [venus_dec] returned 0 after 8203 usecs
[ 19.466991] initcall qcom_venus_enc_driver_init+0x0/0x1000 [venus_enc] returned 0 after 10972 usecs
[ 19.515131] ath: EEPROM regdomain: 0x6c
[ 19.515134] ath: EEPROM indicates we should expect a direct regpair map
[ 19.515139] ath: Country alpha2 being used: 00
[ 19.515141] ath: Regpair used: 0x6c
[ 19.523182] calling arc4_init+0x0/0x1000 [arc4] @ 3513
[ 19.526087] initcall arc4_init+0x0/0x1000 [arc4] returned 0 after 2819 usecs
[ 19.544525] ath10k_pci 0000:01:00.0 wlp1s0: renamed from wlan0
[ 19.742465] initcall panel_driver_init+0x0/0x1000 [panel_boe_himax8279d] returned 0 after 325501 usecs
[ 20.061379] msm_dsi 994000.dsi: 994000.dsi supply gdsc not found, using dummy regulator
[ 20.062037] [drm:msm_dsi_host_init [msm]] dsi_get_config: Version 3:10040001
[ 20.062037]
[ 20.068525] msm_dsi 994000.dsi: Using legacy clk name binding. Use “mdp_core” instead of “mdp_core_clk”
[ 20.076946] msm_dsi 994000.dsi: Using legacy clk name binding. Use “mmagic_iface” instead of “mmagic_iface_clk”
[ 20.086452] msm_dsi 994000.dsi: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 20.096629] msm_dsi 994000.dsi: Using legacy clk name binding. Use “bus” instead of “bus_clk”
[ 20.105395] msm_dsi 994000.dsi: Using legacy clk name binding. Use “byte” instead of “byte_clk”
[ 20.114006] msm_dsi 994000.dsi: Using legacy clk name binding. Use “pixel” instead of “pixel_clk”
[ 20.122938] msm_dsi 994000.dsi: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 20.131816] [drm:msm_dsi_host_init [msm]] Dsi Host 0 initialized
[ 20.140825] [drm:msm_dsi_runtime_resume [msm]] id=0
[ 20.146624] Probe hx8279d
[ 20.159570] [drm:dsi_host_attach [msm]] id=0
[ 20.163784] msm 900000.mdss: bound 994000.dsi (ops dsi_ops [msm])
[ 20.168140] [drm:msm_hdmi_bind [msm]] failed to get gpio: qcom,hdmi-tx-ddc-clk (-2)
[ 20.174056] [drm:msm_hdmi_bind [msm]] failed to get gpio: qcom,hdmi-tx-ddc-data (-2)
[ 20.181523] [drm:msm_hdmi_bind [msm]] failed to get gpio: qcom,hdmi-tx-hpd (-2)
[ 20.189509] [drm:msm_hdmi_bind [msm]] failed to get gpio: qcom,hdmi-tx-mux-en (-2)
[ 20.196539] [drm:msm_hdmi_bind [msm]] failed to get gpio: qcom,hdmi-tx-mux-sel (-2)
[ 20.204175] [drm:msm_hdmi_bind [msm]] failed to get gpio: qcom,hdmi-tx-mux-lpm (-2)
[ 20.212286] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “iface” instead of “iface_clk”
[ 20.219353] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “core” instead of “core_clk”
[ 20.228751] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “mdp_core” instead of “mdp_core_clk”
[ 20.233469] systemd-journald[2425]: Successfully sent stream file descriptor to service manager.
[ 20.248119] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “extp” instead of “extp_clk”
[ 20.256866] hdmi_msm 9a0000.hdmi-tx: Using legacy clk name binding. Use “alt_iface” instead of “alt_iface_clk”
[ 20.266233] [drm:msm_dsi_runtime_suspend [msm]]
Starting Run pending postinsts…
[ 20.276603] msm 900000.mdss: bound 9a0000.hdmi-tx (ops msm_hdmi_ops [msm])
[ 20.276771] [drm:adreno_bind [msm]] Found GPU: 5.3.0.2
[ 20.276817] [drm:adreno_gpu_init [msm]] fast_rate=624000000, slow_rate=27000000, bus_freq=0
[ 20.277043] [drm:msm_gpu_init [msm]] ebi1_clk: fffffffffffffffe
[ 20.277094] adreno b00000.gpu: b00000.gpu supply vdd not found, using dummy regulator
[ 20.277163] [drm:msm_gpu_init [msm]] gpu_reg: ffff8000f3b24c00
[ 20.277195] adreno b00000.gpu: b00000.gpu supply vddcx not found, using dummy regulator
[ 20.277259] [drm:msm_gpu_init [msm]] gpu_cx: ffff8000f3b24e00
[ 20.277262] msm 900000.mdss: A530: using IOMMU
[ 20.277333] [drm:msm_gpu_pm_resume [msm]] A530
[ 20.278687] msm 900000.mdss: bound b00000.gpu (ops a3xx_ops [msm])
[ 20.278914] [drm:mdp5_runtime_resume [msm]]
[ 20.278960] [drm:mdp5_enable [msm]]
[ 20.285763] calling hdmi_codec_driver_init+0x0/0x1000 [snd_soc_hdmi_codec] @ 2678
[ 20.306672] [drm:mdp5_runtime_suspend [msm]]
[ 20.306718] [drm:mdp5_disable [msm]]
[ 20.306772] [drm:mdp5_ctlm_request [msm]] CTL 0 allocated
[ 20.306948] [drm:mdp5_runtime_resume [msm]]
[ 20.306994] [drm:mdp5_enable [msm]]
[ 20.307062] [drm:mdp5_ctlm_request [msm]] CTL 2 allocated
[ 20.307159] [drm:msm_hdmi_hpd_enable [msm]] gpio on
[ 20.307218] [drm:msm_hdmi_set_mode [msm]] HDMI Core: Disable, HDMI_CTRL=0x00000003
[ 20.346078] systemd-journald[2425]: Successfully sent stream file descriptor to service manager.
[ 20.437078] systemd-journald[2425]: Successfully sent stream file descriptor to service manager.
[ 20.437834] systemd-journald[2425]: Successfully sent stream file descriptor to service manager.
[ 20.453902] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 20.453904] [drm] Driver supports precise vblank timestamp query.
[ 20.469184] [drm:drm_setup_crtcs [drm_kms_helper]]
[ 20.469277] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:28:DSI-1]
[ 20.469451] [drm:dsi_mgr_connector_detect [msm]] id=0
[ 20.469481] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:28:DSI-1] status updated from unknown to connected
[ 20.469484] Panel selected: boe,himax8279d8p
[ 20.469485] Mode selected= Height: 800 x Width: 1280
[ 20.469541] [drm:dsi_mgr_connector_mode_valid [msm]]
[ 20.469587] [drm:dsi_mgr_connector_mode_valid [msm]] requested=71980000, actual=71980000
[ 20.469622] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:28:DSI-1] probed modes :
[ 20.469793] [drm:drm_mode_debug_printmodeline [drm]] Modeline 58:“800x1280” 60 71980 800 872 896 920 1280 1292 1294 1304 0x0 0x0
[ 20.469818] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:30:HDMI-A-1]
[ 20.469851] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:30:HDMI-A-1] status updated from unknown to discond
[ 20.469871] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:30:HDMI-A-1] disconnected
[ 20.469892] [drm:drm_setup_crtcs [drm_kms_helper]] connector 28 enabled? yes
[ 20.469913] [drm:drm_setup_crtcs [drm_kms_helper]] connector 30 enabled? no
[ 20.469933] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 28
[ 20.469952] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 28 0
[ 20.469970] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 800x1280
[ 20.469988] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 65535x65535 config
[ 20.470055] [drm:dsi_mgr_connector_best_encoder [msm]]
[ 20.470076] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 800x1280 set on crtc 56 (0,0)
[ 20.470127] [drm:msm_fbdev_create [msm]] create fbdev: 800x1280@32 (800x1280)
[ 20.470176] [drm:msm_alloc_stolen_fb [msm]] allocating 4096000 bytes for fb 0
[ 20.470234] [drm:msm_framebuffer_init [msm]] create framebuffer: dev=ffff8000f3bcc000, mode_cmd=ffff00000e1538e8 (800x1280@XR24)
[ 20.470286] [drm:msm_framebuffer_init [msm]] create: FB ID: 60 (ffff8000f72e9600)
[ 20.473533] [drm:msm_fbdev_create [msm]] fbi=ffff8000f718ec00, dev=ffff8000f3bcc000
[ 20.474413] [drm:msm_fbdev_create [msm]] par=ffff8000f87ebe00, 800x1280
[ 20.474460] [drm:msm_fbdev_create [msm]] allocated 800x1280 fb
m…
[ 20.700941] [drm:dsi_mgr_connector_best_encoder [msm]]
[ 20.700990] [drm:dsi_mgr_connector_best_encoder [msm]]
[ 20.701043] [drm:mdp5_plane_atomic_check [msm]] plane-0: check (0 → 0)
[ 20.701094] [drm:mdp5_pipe_assign [msm]] DMA0: assign to plane plane-0 for caps 0
[ 20.701141] [drm:mdp5_crtc_atomic_check [msm]] crtc-0: check
[ 20.701207] [drm:mdp5_mixer_assign [msm]] assigning Layer Mixer 2 to crtc crtc-0
[ 20.701255] [drm:mdp5_crtc_atomic_check [msm]] crtc-0: assign pipe plane-0 on stage=1
[ 20.701303] [drm:mdp5_crtc_atomic_check [msm]] crtc-1: check
[ 20.701352] [drm:mdp5_plane_prepare_fb [msm]] plane-0: prepare: FB[60]
[ 20.701399] [drm:msm_framebuffer_prepare [msm]] FB[60]: iova[0]: 00002000 (0)
[ 20.701452] [drm:msm_atomic_commit [msm]] start: 00000003
[ 20.701507] [drm:mdp5_crtc_mode_set_nofb [msm]] crtc-0: set mode: 0:“800x1280” 60 71980 800 872 896 920 1280 1292 1294 1304 0x0 0x0
[ 20.701560] [drm:dsi_mgr_bridge_mode_set [msm]] set mode: 0:“800x1280” 60 71980 800 872 896 920 1280 1292 1294 1304 0x0 0x0
[ 20.701607] [drm:mdp5_crtc_atomic_begin [msm]] crtc-0: begin
[ 20.701654] [drm:mdp5_crtc_atomic_begin [msm]] crtc-1: begin
[ 20.701699] [drm:mdp5_plane_atomic_update [msm]] plane-0: update
[ 20.701747] [drm:mdp5_plane_mode_set.isra.0 [msm]] plane-0: FB[60] 0,0,800,1280 → CRTC[56] 0,0,800,1280
[ 20.701793] [drm:mdp5_plane_mode_set.isra.0 [msm]] scale config = 0
[ 20.701855] [drm:mdp5_hwpipe_mode_set.isra.0.constprop.0 [msm]] comp-0 (L/R): rpt=0/0, ovf=0/0, req=800
[ 20.701900] [drm:mdp5_hwpipe_mode_set.isra.0.constprop.0 [msm]] comp-0 (T/B): rpt=0/0, ovf=0/0, req=1280
[ 20.701949] [drm:mdp5_hwpipe_mode_set.isra.0.constprop.0 [msm]] comp-1 (L/R): rpt=0/0, ovf=0/0, req=800
[ 20.701995] [drm:mdp5_hwpipe_mode_set.isra.0.constprop.0 [msm]] comp-1 (T/B): rpt=0/0, ovf=0/0, req=1280
[ 20.702044] [drm:mdp5_hwpipe_mode_set.isra.0.constprop.0 [msm]] comp-2 (L/R): rpt=0/0, ovf=0/0, req=800
[ 20.702089] [drm:mdp5_hwpipe_mode_set.isra.0.constprop.0 [msm]] comp-2 (T/B): rpt=0/0, ovf=0/0, req=1280
[ 20.702146] [drm:mdp5_crtc_atomic_flush [msm]] crtc-0: event: (null)
[ 20.702218] [drm:mdp5_ctl_blend [msm]] lm2: blend config = 0x00040000. ext_cfg = 0x00000000
[ 20.702265] [drm:crtc_flush.isra.0 [msm]] crtc-0: flush=00000900
[ 20.702320] [drm:mdp5_crtc_atomic_flush [msm]] crtc-1: event: (null)
[ 20.702367] [drm:mdp5_crtc_atomic_enable [msm]] crtc-0
[ 20.702425] [drm:mdp5_crtc_mode_set_nofb [msm]] crtc-0: set mode: 0:“800x1280” 60 71980 800 872 896 920 1280 1292 1294 1304 0x0 0x0
[ 20.702479] [drm:dsi_mgr_bridge_pre_enable [msm]] id=0
[ 20.702524] [drm:msm_dsi_host_reset_phy [msm]]
[ 20.703674] [drm:msm_dsi_host_get_phy_clk_req [msm]] pclk=71980000, bclk=53985000
[ 20.703722] [drm:msm_dsi_phy_enable [msm]]
[ 20.703773] [drm:msm_dsi_dphy_timing_calc_v2 [msm]] 29, 10, 0, 13, 5, 4, 30, 27, 4, 6, 2, 2, 0, 0, 0, 0
[ 20.704040] [drm:msm_dsi_host_power_on [msm]]
[ 20.708578] [drm:msm_dsi_runtime_resume [msm]] id=0
[ 20.708631] [drm:dsi_link_clk_enable [msm]] Set clk rates: pclk=71980, byteclk=53985000
[ 20.708681] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=431880000
[ 20.708745] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=431880000
[ 20.708789] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=431880000
[ 20.708833] [drm:dsi_pll_14nm_postdiv_recalc_rate [msm]] DSI0 PLL parent rate=1727520000
[ 20.708880] [drm:dsi_pll_14nm_postdiv_recalc_rate [msm]] DSI0 PLL parent rate=863760000
[ 20.708934] [drm:dsi_pll_14nm_postdiv_recalc_rate [msm]] DSI0 PLL parent rate=215940000
[ 20.708986] [drm:dsi_pll_14nm_vco_set_rate [msm]] DSI PLL0 rate=1727520000, parent’s=19200000
[ 20.709030] [drm:dsi_pll_14nm_vco_set_rate [msm]] vco_clk_rate=1727520000 ref_clk_rate=19200000
[ 20.709074] [drm:dsi_pll_14nm_vco_set_rate [msm]] vco=1727520000 ref=19200000
[ 20.709117] [drm:dsi_pll_14nm_vco_set_rate [msm]] ssc freq=31500 spread=5 period=304
[ 20.709160] [drm:dsi_pll_14nm_vco_set_rate [msm]] step_size=58773
[ 20.709226] [drm:pll_db_commit_14nm [msm]] DSI0 PLL
[ 20.709338] [drm:dsi_pll_14nm_vco_recalc_rate [msm]] dec_start = 59
[ 20.709386] [drm:dsi_pll_14nm_vco_recalc_rate [msm]] div_frac_start = f9999
[ 20.709429] [drm:dsi_pll_14nm_vco_recalc_rate [msm]] returning vco rate = 1727520000
[ 20.709473] [drm:dsi_pll_14nm_postdiv_set_rate [msm]] DSI0 PLL parent rate=431880000 parent rate 1727520000
[ 20.709521] [drm:dsi_pll_14nm_postdiv_recalc_rate [msm]] DSI0 PLL parent rate=1727520000
[ 20.709567] [drm:dsi_pll_14nm_postdiv_set_rate [msm]] DSI0 PLL parent rate=14396000 parent rate 215940000
[ 20.709615] [drm:dsi_pll_14nm_postdiv_recalc_rate [msm]] DSI0 PLL parent rate=215940000
[ 20.709683] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=191946666
[ 20.709727] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=323910000
[ 20.709770] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=161955000
[ 20.709813] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=71980000
[ 20.709859] [drm:dsi_pll_14nm_postdiv_round_rate [msm]] DSI0 PLL parent rate=71980000
[ 20.709907] [drm:dsi_pll_14nm_postdiv_set_rate [msm]] DSI0 PLL parent rate=71980000 parent rate 215940000
[ 20.709954] [drm:dsi_pll_14nm_postdiv_recalc_rate [msm]] DSI0 PLL parent rate=215940000
[ 20.710014] [drm:dsi_pll_14nm_enable_seq [msm]]
[ 20.711064] [drm:dsi_pll_14nm_enable_seq [msm]] DSI PLL is locked
[ 20.711106] [drm:dsi_pll_14nm_enable_seq [msm]] DSI PLL lock success
[ 20.711149] [drm:msm_dsi_pll_helper_clk_prepare [msm]] DSI PLL locked after sequence #1
[ 20.711201] [drm:msm_dsi_host_power_on [msm]]
[ 20.711267] [drm:dsi_intr_ctrl [msm]] intr=a220aa02 enable=1
[ 20.711314] [drm:msm_dsi_host_power_on [msm]] lane number=4
[ 20.711321] Prepare hx8279d

It looks like drm is loaded but not by msm.
Any ideas how to solve this?