Increasing i2s0 hikey capture rate


Currently i2s0 capture rate is max at 48Khz on hikey960. On hikey970, the supported capture rate is upto 192 Khz. as per file sound/soc/hisilicon/hi6210-i2s.c
switch (params_rate(params)) {
case 8000:
rate = HII2S_FS_RATE_8KHZ;
case 16000:
rate = HII2S_FS_RATE_16KHZ;
case 32000:
rate = HII2S_FS_RATE_32KHZ;
case 48000:
rate = HII2S_FS_RATE_48KHZ;
case 96000:
rate = HII2S_FS_RATE_96KHZ;
case 192000:
rate = HII2S_FS_RATE_192KHZ;
dev_err(cpu_dai->dev, “Bad rate: %d\n”, params_rate(params));
return -EINVAL;

in hikey960,we change 48k frequency i2s0 freqency to other frequencies by modifying
hisi_syscon_bits(i2s, HI_ASP_CFG_R_CLK3_DIV_REG, HI_ASP_MASK,
where , HI_ASP_CFG_R_CLK4_DIV_SEL can be replaced by
#define HI_ASP_CFG_R_CLK4_DIV_SEL_3M 0x00ff000f // 48K freqeuncy
#define HI_ASP_CFG_R_CLK4_DIV_SEL_1M 0x00ff002f // 16K frequency
#define HI_ASP_CFG_R_CLK4_DIV_SEL_512K 0x00ff005f // 8K freqeuncy

How can I change FS frequency to 96khz or 192 khz for capturing audio at those sample rates? Can someone please tell me what should be the value of HI_ASP_CFG_R_CLK4_DIV_SEL?


When I came up with those numbers (2f and 5f), I did so by trial and error with a logic probe to measure the resulting frame clock.

In order to go to a higher FS, you will need either a smaller divider, or a higher master clock. My suspicion, since the divider is already pretty small (0xf), you probably won’t get good results unless you increase the master clock. That would likely be via CLK1 rather than CLK4. Don’t ask me where the number it has comes from, I have no idea.

Any particular reason you’re going to a higher sample rate? Scientific measurements? For general audio hardware, I’m not aware of anyone (besides maybe my dog) that can actually tell the difference after you break 40k.

And FWIW: The 970 and 960 are pretty much the same SoC. The 6210 is for the original hikey, not the 970.


0x00ff0007,How can I change BCLK from I2S2? I need higher speed.