I2c on LS Expansion connector


#1

Hi all I am not having any luck connecting to i2c on the LS Expansion connector.

I am using the current 15.07 release.

i2cdetect only sees 1 bus:

linaro@linaro-alip:~$ sudo i2cdetect -l
i2c-0	i2c       	QUP I2C adapter                 	I2C adapter

This is confirmed when looking at sysfs

linaro@linaro-alip:~$ ll /sys/bus/i2c/devices/
total 0
drwxr-xr-x 2 root root 0 Sep 22 22:36 ./
drwxr-xr-x 4 root root 0 Sep 22 22:36 ../
lrwxrwxrwx 1 root root 0 Jan  1  1970 0-0039 -> ../../../devices/platform/soc/78b8000.i2c/i2c-0/0-0039/
lrwxrwxrwx 1 root root 0 Jan  1  1970 0-003c -> ../../../devices/platform/soc/78b8000.i2c/i2c-0/0-003c/
lrwxrwxrwx 1 root root 0 Jan  1  1970 0-003f -> ../../../devices/platform/soc/78b8000.i2c/i2c-0/0-003f/
lrwxrwxrwx 1 root root 0 Jan  1  1970 i2c-0 -> ../../../devices/platform/soc/78b8000.i2c/i2c-0/

I connected a scope to ic20_scl (pin 15) and also to i2c1_scl (pin 19) but I do not see any activity on either pin while probing them with i2cdetect (i.e sudo i2cdetect -y -r 0).

How do I enable the i2c bus(es) on the LS expansion connector?

thanks


#2

One thing to add. I am using a custom kernel based on the 15.07 release and do have i2c-dev enabled:

linaro@linaro-alip:~$ grep "kernel/drivers/i2c" /lib/modules/4.0.0/modules.builtin
kernel/drivers/i2c/i2c-core.ko
kernel/drivers/i2c/i2c-dev.ko
kernel/drivers/i2c/i2c-mux.ko
kernel/drivers/i2c/algos/i2c-algo-bit.ko
kernel/drivers/i2c/busses/i2c-qup.ko

#3

Hi,

In the Linux release 15.07, there is only one bus configured on which ADV7533 is connected.
so when you perform i2cdetect -y -r 0,
you will surely get activity on it’s i2c0_scl and i2c0_sda lines.

and if you want to enable another i2c bus, you have to configure it in it’s msm8916.dtsi and apq8016-sbc.dtsi files.

thanks.


#4

Thanks for the response deep123. I definitely do not see any activity on the LS Expansion connector using a scope.

In looking at the files you suggested (msm8916.dtsi and msm8916-pins.dtsi), I only see i2c4 defined and it points to GPIO14 and 15 which the schematics doc (http://linaro.co/db410c-schematics pages 5 and 29) says are i2c3_sda and i2c3_scl and are on the HS Connector not the LS one.

I’ll try to create entries in the dtsi for the i2c on the LS and see what happens. The msm8916-pins.dtsi looks straight forward, the msm8916.dtsi not so much. Do you know what I need to set the reg, interrupts and clocks parameters for blsp_i2c1 and/or blsp_i2c2? Thanks.


#5

Hi,

you can refer Peripherals programming guide on this below link and refer I2c section.

thanks


#6

Making some progress but still confused.

I added the following under msm_gpio in arch/arm64/boot/dts/qcom/msm8916.dtsi:

                        i2c1_default: i2c1_default {
                                pinmux {
                                        function = "blsp_i2c1";
                                        pins = "gpio6", "gpio7";
                                };
                                pinconf {
                                        pins = "gpio6", "gpio7";
                                        drive-strength = <2>;
                                        bias-disable = <0>;
                                };
                        };

                        i2c1_sleep: i2c1_sleep {
                                pinmux {
                                        function = "blsp_i2c1";
                                        pins = "gpio6", "gpio7";
                                };
                                pinconf {
                                        pins = "gpio6", "gpio7";
                                        drive-strength = <2>;
                                        bias-disable = <0>;
                                };
                        };

                        i2c2_default: i2c2_default {
                                pinmux {
                                        function = "blsp_i2c2";
                                        pins = "gpio22", "gpio23";
                                };
                                pinconf {
                                        pins = "gpio22", "gpio23";
                                        drive-strength = <2>;
                                        bias-disable = <0>;
                                };
                        };

                        i2c2_sleep: i2c2_sleep {
                                pinmux {
                                        function = "blsp_i2c2";
                                        pins = "gpio22", "gpio23";
                                };
                                pinconf {
                                        pins = "gpio22", "gpio23";
                                        drive-strength = <2>;
                                        bias-disable = <0>;
                                };
                        };

and the following under soc:

                blsp_i2c2: i2c@78b5000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x78b5000 0x1000>;
                        interrupts = <GIC_SPI 95 0>;
                        clocks = <&gcc GCC_BLSP1_AHB_CLK>,
                                <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
                        clock-names = "iface", "core";
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c1_default>;
                        pinctrl-1 = <&i2c1_sleep>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };

                blsp_i2c6: i2c@78b6000 {
                        compatible = "qcom,i2c-qup-v2.2.1";
                        reg = <0x78b6000 0x1000>;
                        interrupts = <GIC_SPI 96 0>;
                        clocks = <&gcc GCC_BLSP1_AHB_CLK>,
                                <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
                        clock-names = "iface", "core";
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&i2c2_default>;
                        pinctrl-1 = <&i2c2_sleep>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
                };

I then set the status to “ok” in arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi for both blsp_i2c1 and 2 to match the way it was done with blsp_i2c4.

After flashing the new boot image things looked and the i2c entries showed up but were not working properly and this is what I saw in dmesg:

[    2.091315] i2c /dev entries driver
[    2.095687] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio6" for function "blsp_i2c1"
[    2.098563] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio7" for function "blsp_i2c1"
[    2.106928] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio6" for function "blsp_i2c1"
[    2.115247] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio7" for function "blsp_i2c1"
[    2.123660] i2c_qup 78b5000.i2c: 
 tx channel not available
[    2.133821] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio22" for function "blsp_i2c2"
[    2.138842] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio23" for function "blsp_i2c2"
[    2.147553] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio22" for function "blsp_i2c2"
[    2.155957] msm8916-pinctrl 1000000.pinctrl: invalid group "gpio23" for function "blsp_i2c2"
[    2.164445] i2c_qup 78b6000.i2c: 
 tx channel not available
[    2.174067] i2c_qup 78b8000.i2c: 
 tx channel not available

Digging around the sys fs I found the following:

linaro@linaro-alip:~$ sudo grep blsp_i2c /sys/kernel/debug/pinctrl/1000000.pinctrl/pinmux-functions 
function: blsp_i2c1, groups = [ gpio2 gpio3 ]
function: blsp_i2c2, groups = [ gpio6 gpio7 ]
function: blsp_i2c3, groups = [ gpio10 gpio11 ]
function: blsp_i2c4, groups = [ gpio14 gpio15 ]
function: blsp_i2c5, groups = [ gpio18 gpio19 ]
function: blsp_i2c6, groups = [ gpio22 gpio23 ]

So based on this I changed the function names (i.e. blsp_i2cX) in the pinctrls (but left the pinctrl names --ie i2cX_default/sleep-- the same) and also changed the names of the blsp_i2cX entries in the soc section. I left the core clock the same as it matched the physical address as described in the Peripherals programing guide.

After this change the dmesg error went away and things are kind of working but here is where my confusion comes from. The devices show up in sys fs:

linaro@linaro-alip:~$ ls -al /sys/bus/i2c/devices/i2c-*
lrwxrwxrwx 1 root root 0 Sep 23 23:10 /sys/bus/i2c/devices/i2c-0 -> ../../../devices/platform/soc/78b5000.i2c/i2c-0
lrwxrwxrwx 1 root root 0 Sep 23 23:10 /sys/bus/i2c/devices/i2c-1 -> ../../../devices/platform/soc/78b6000.i2c/i2c-1
lrwxrwxrwx 1 root root 0 Sep 23 23:10 /sys/bus/i2c/devices/i2c-2 -> ../../../devices/platform/soc/78b8000.i2c/i2c-2

And they appear to point to the correct physical address but in practice the pins for i2c0 as described in the schematics (ie. gpio6 and 7) are the ones responding to i2cbus 1 using i2cdetect which seems incorrect based on the above. i2cbus 0 responds extremely slow using i2cdetect.

Is the problem that I didn’t remain consistent with the naming of the pin controls? Should I switch pinctrl names and physical address to match the pinmux-functions?

thanks


#7

I redid my work and it is working properly now. I have both i2c buses on the LS Expansion Connector working.

Here is the diff for my changes based on 15.07 release:

diff --git arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 82cdb72..1d22af9 100644
--- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -161,6 +161,14 @@
 	pinctrl-0 = <&usb_sw_sel_pm_default>;
 };
 
+&blsp_i2c6 {
+	status = "ok";
+};
+
+&blsp_i2c2 {
+	status = "ok";
+};
+
 &blsp_i2c4 {
 	status = "ok";
 };
diff --git arch/arm64/boot/dts/qcom/msm8916.dtsi arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0204e0e..516727c 100644
--- arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -492,6 +492,54 @@
 				};
 			};
 
+			i2c2_default: i2c2_default {
+				pinmux {
+					function = "blsp_i2c2";
+					pins = "gpio6", "gpio7";
+				};
+				pinconf {
+					pins = "gpio6", "gpio7";
+					drive-strength = <2>;
+					bias-disable = <0>;
+				};
+			};
+
+			i2c2_sleep: i2c2_sleep {
+				pinmux {
+					function = "blsp_i2c2";
+					pins = "gpio6", "gpio7";
+				};
+				pinconf {
+					pins = "gpio6", "gpio7";
+					drive-strength = <2>;
+					bias-disable = <0>;
+				};
+			};
+
+			i2c6_default: i2c6_default {
+				pinmux {
+					function = "blsp_i2c6";
+					pins = "gpio22", "gpio23";
+				};
+				pinconf {
+					pins = "gpio22", "gpio23";
+					drive-strength = <2>;
+					bias-disable = <0>;
+				};
+			};
+
+			i2c6_sleep: i2c6_sleep {
+				pinmux {
+					function = "blsp_i2c6";
+					pins = "gpio22", "gpio23";
+				};
+				pinconf {
+					pins = "gpio22", "gpio23";
+					drive-strength = <2>;
+					bias-disable = <0>;
+				};
+			};
+
 			i2c4_default: i2c4_default {
 				pinmux {
 					function = "blsp_i2c4";
@@ -1174,6 +1222,36 @@
 			status = "disabled";
 		};
 
+		blsp_i2c2: i2c@78b6000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x78b6000 0x1000>;
+			interrupts = <GIC_SPI 96 0>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&i2c2_default>;
+			pinctrl-1 = <&i2c2_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		blsp_i2c6: i2c@78ba000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x78ba000 0x1000>;
+			interrupts = <GIC_SPI 100 0>;
+			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+			clock-names = "iface", "core";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&i2c6_default>;
+			pinctrl-1 = <&i2c6_sleep>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		blsp_i2c4: i2c@78b8000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			reg = <0x78b8000 0x1000>;