How to interface memory to programmable logic in Avnet Ultra96 FPGA Board

I am mapping a RISC V SoC to Ultra96 FPGA Board. I want to interface the 2GB LPDDR4 Memory present on the board to the RISC V Core that I implemented on the Programmable Logic. There is no Memory Interface Generator (MIG) available for Zynq Ultrascale+ MPSoC. Can anyone please help me with this?

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The LPDDR4 on Ultra96 is physically tied to the Processing System I/O pins, which are not accessible to the Programmable Logic. Therefore, it is not possible to connect a soft processor in the PL to the on-board LPDDR4.
Bryan