Hi there,
We’ve successfully utilised the MIPI DSI interface configured for a single lane to drive a 300x300 with the following configuration:
static const struct drm_display_mode default_mode = {
.clock = 9764,
.hdisplay = 350,
.hsync_start = 350 + 20,
.hsync_end = 350 + 20 + 26,
.htotal = 350 + 20 + 26 + 30,
.vdisplay = 350,
.vsync_start = 350 + 16,
.vsync_end = 350 + 16 + 4,
.vtotal = 350 + 16 + 4 + 12,
.vrefresh = 60,
};
However, for our application requirements, we require an extremely large vertical front and back porch i.e:
static const struct drm_display_mode default_mode = {
.clock = 25100,
.hdisplay = 350,
.hsync_start = 350 + 20,
.hsync_end = 350 + 20 + 26,
.htotal = 350 + 20 + 26 + 30,
.vdisplay = 350,
.vsync_start = 350 + 316,
.vsync_end = 350 + 316 + 4,
.vtotal = 350 + 316 + 4 + 312,
.vrefresh = 60,
};
In this config we are using a pix clk of 25.1MHz, byte clock of 75.3MHz and MIPI DSI link rate of 602.4Mbps (MIPI link rate 301.2MHz).
However, in this case, we get corrupted data on the display (i.e. bottom quarter of screen is missing as well as a lot of tearing).
I was wondering if there was any limitation on frame configuration when using a 1-lane MIPI DSI interface on the APQ8016E.
Many thanks,
