Hi All,
I have an Open-q 410 board from Intrinsyc (very similar to dragonboard 410 in terms of SoC and other modules).
I am attempting to configure some BLSP pins as GPIOs, but am having some issues getting this working as I expect it to. Hopefully someone here can point me in the right direction 
What I am currently attempting to do:
- Configure BLSP30 (GPIO11) as a GPIO setup as active low, and default state high.
- Branching off tag
debian-qcom-dragonboard410c-19.01
What I have done so far:
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index aac1da4f1d3c..b7f256375dc0 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -28,7 +28,7 @@
i2c1 = &blsp_i2c6;
i2c3 = &blsp_i2c4;
spi0 = &blsp_spi5;
- spi1 = &blsp_spi3;
+ // spi1 = &blsp_spi3;
};
chosen {
@@ -79,7 +79,7 @@
status = "okay";
adv_bridge: bridge@39 {
- status = "okay";
+ status = "disabled";
compatible = "adi,adv7533";
reg = <0x39>;
@@ -193,6 +193,17 @@
};
};
+ srs_gpios {
+ pinctrl-0 = <&msmgpio_enable>;
+
+ srs_gpio@1 {
+ label = "ublox-power";
+ gpios = <&msmgpio 11 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+
+
sdhci@07824000 {
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
@@ -239,7 +250,7 @@
};
mdss@1a00000 {
- status = "okay";
+ status = "disabled";
mdp@1a01000 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index 21d0822f1ca6..6795e3ecd297 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -4,6 +4,19 @@
&msmgpio {
+ msmgpio_enable: msmgpio_enable {
+ pinmux {
+ pins = "gpio11";
+ function = "gpio";
+ };
+ pinconf {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 34d4b00e5c61..74528d223200 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -458,22 +458,22 @@
status = "disabled";
};
- blsp_spi3: spi@78b7000 {
- compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078b7000 0x600>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
- <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
- dmas = <&blsp_dma 9>, <&blsp_dma 8>;
- dma-names = "rx", "tx";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&spi3_default>;
- pinctrl-1 = <&spi3_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
+ // blsp_spi3: spi@78b7000 {
+ // compatible = "qcom,spi-qup-v2.2.1";
+ // reg = <0x078b7000 0x600>;
+ // interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ // clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+ // <&gcc GCC_BLSP1_AHB_CLK>;
+ // clock-names = "core", "iface";
+ // dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ // dma-names = "rx", "tx";
+ // pinctrl-names = "default", "sleep";
+ // pinctrl-0 = <&spi3_default>;
+ // pinctrl-1 = <&spi3_sleep>;
+ // #address-cells = <1>;
+ // #size-cells = <0>;
+ // status = "disabled";
+ // };
blsp_spi4: spi@78b8000 {
compatible = "qcom,spi-qup-v2.2.1";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index b1ed8dcf7543..ea7ba876533a 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -134,39 +134,39 @@
};
};
- spi3_default: spi3_default {
- pinmux {
- function = "blsp_spi3";
- pins = "gpio8", "gpio9", "gpio11";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio10";
- };
- pinconf {
- pins = "gpio8", "gpio9", "gpio11";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio10";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- spi3_sleep: spi3_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- };
- pinconf {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
+ // spi3_default: spi3_default {
+ // pinmux {
+ // function = "blsp_spi3";
+ // pins = "gpio8", "gpio9", "gpio11";
+ // };
+ // pinmux_cs {
+ // function = "gpio";
+ // pins = "gpio10";
+ // };
+ // pinconf {
+ // pins = "gpio8", "gpio9", "gpio11";
+ // drive-strength = <12>;
+ // bias-disable;
+ // };
+ // pinconf_cs {
+ // pins = "gpio10";
+ // drive-strength = <16>;
+ // bias-disable;
+ // output-high;
+ // };
+ // };
+
+ // spi3_sleep: spi3_sleep {
+ // pinmux {
+ // function = "gpio";
+ // pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ // };
+ // pinconf {
+ // pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ // drive-strength = <2>;
+ // bias-pull-down;
+ // };
+ // };
Note: I commented out the spi3 configuration just in case it would clash with gpio setup (as they both use gpio11). I realise spi3 is disabled by default, but it wasnāt working before I commented this out either so I just tried it.
I build the device tree based on the documentation at 96boards and use fastboot to flash the new boot-db410.img
I am attempting to test the GPIO funcionality following these instructions (using sysfs)
ie.
cd /sys/class/gpio
echo 11 > export
cd gpio11
cat direction //'in' by default
echo out > direction
cat value //'0' by default
echo 1 > value
While doing this I am measuring the appropriate pin with an oscilloscope, but the voltage remains at 1.8V the entire time.
As a side note, I noticed the dragonboard 410 documentation mentions the some pins are set as GPIOs by default DragonBoard410c: 36, 12, 13, 69, 115, 4, 24, 25, 35, 34, 28, 33. I am unable to find where/how these may be set up in the device tree thoughā¦
Any help here would be appreciatedā¦ potentially relating to mistakes in my device tree configuration, and also on how I can verify my changes are taking effect when the board has booted.
