Could not enter u-boot shell

Products Support Bubblegum-96
#1

Hi,
I bought a bubblegum-96 board from taobao, no UART debug board was provided. So I used USB UART converter to connect PIN 1, 11, 13 for UART output.
I tried to use fastboot method to install debian OS. I am able to enter ADFU mode, but could NOT enter u-boot shell(“owl>”) by hitting button at serial console after executing “sudo linaro-adfu-tool-bg96 u-boot-dtb.img”.
My output from serial console was shown in below:

adfu: <INFO>adfusever: ver 1.0-906dfed (build Mar 11 2016 16:16:46)
atc260x_early_init bus_num:3, bus_mfp:0
owl_i2c_init bus_num:3, bus_mfp:0
PMU:found PMIC type 2 ver 3
PMU:dat = 0x5a78!!!
PMU:RTC acc closed!!!
PMU:PMU_SYS_CTL0 0xe0d5, CTL1 0x4017, CTL2 0x680, CTL3 0x4000
adfu: <INFO>adfusever 174
adfu: <INFO>adfusever 177
clock_get = 552 mz
[DDR] ddr_clk 0x228
[DDR] ddr_type 0x2
[DDR] ddr_single_cap 0x5
[DDR] ddr_width 0x0
[DDR] rank 0x0
[DDR] dual_chan 0x2
[DDR] clk_drv 0x99
[DDR] ca_drv 0xdd
[DDR] dram_odt_en 0x0
[DDR] twls_adj 0x0
[DDR] pad_tsel 0x3ddf77dd
cs map value 3 !
DDR PHY PLL not lock!
DDR PHY PLL locked!
cs map value 3 !
DDR PHY PLL not lock!
DDR PHY PLL locked!
channel 0 init_start processing!
channel 0 init_start pass!
channel 1 init_start processing!
channel 1 init_start pass!
biststart_dualchannel start!
cs map value 3 !
DDR PHY PLL not lock!
DDR PHY PLL locked!
cs map value 3 !
DDR PHY PLL not lock!
DDR PHY PLL locked!
channel 0 init_start processing!
channel 0 init_start pass!
channel 1 init_start processing!
channel 1 init_start pass!
cs map value 3 !
DDR PHY PLL not lock!
DDR PHY PLL locked!
cs map value 3 !
DDR PHY PLL not lock!
DDR PHY PLL locked!
channel 0 init_start processing!
channel 0 init_start pass!
channel 1 init_start processing!
channel 1 init_start pass!
0x40000000!
DDR capacity is 2GB!
DMM_INTERLEAVE_PER_CH_CFG: 52d
[DDR produce] save param clk 552 Mhz
adfu: <INFO>adfusever 182
adfu: <INFO>adfusever 187
dwc3:owl_dwc3_init 184 Mar 11 2016 16:16:42
adfu: <INFO>adfusever 199
adfu: <INFO>UsbOtgEp1OutDeal: my_cbw.sCbw.cCBWCB[0] is 0x13!
adfu: <INFO>my_access_internal_ram: direction is 0, ram_addr is adfu: <INFO>UsbOtgEp1OutDeal: my_cbw.sCbw.cCBWCB[0] is 0x13!
adfu: <INFO>my_access_internal_ram: direction is 0, ram_addr is adfu: <INFO>UsbOtgEp1OutDeal: my_cbw.sCbw.cCBWCB[0] is 0x13!
adfu: <INFO>my_access_internal_ram: direction is 0, ram_addr is adfu: <INFO>UsbOtgEp1OutDeal: my_cbw.sCbw.cCBWCB[0] is 0x20!
adfu: <INFO>my_switch_fw: ram_addr is 0xversion = 0x100
bond = 0x0
read redundancy over
the chipid_ctrl is 0x0
the chipid_ctrl is 0x4
the chipid_ctrl is 0x8
the chipid_ctrl is 0xc
dvfs find
the return dvfslevel is 0xd7729580
adfu: <INFO>while: SWTICH_FW ==>>!
adfu: <INFO>cpu init
adfu: <INFO>cpu switch_to_el2 0x1f000000
mmap_add_region: base_pa 0x1f000000, base_va 0x1f000000 size 0x1a000, attr 0x3
mmap_add_region: base_pa 0x1f000000, base_va 0x1f000000 size 0x10000, attr 0x1
mmap_add_region: base_pa 0x1f019000, base_va 0x1f019000 size 0x1000, attr 0x2
mmap_add_region: base_pa 0x1f200000, base_va 0x1f200000 size 0x800000, attr 0x3
mmap_add_region: base_pa 0xe0000000, base_va 0xe0000000 size 0x800000, attr 0x2
mmap_add_region: base_pa 0x0, base_va 0x0 size 0x1f000000, attr 0x7
NOTICE: BL3-1: v1.0(debug):ce09c60
NOTICE: BL3-1: Built : 17:28:04, Sep 7 2015PMU:found PMIC type 2 ver 3
INFO: BL3-1: Initializing runtime services
INFO: BL3-1: Initializing BL3-2
mmap_add_region: base_pa 0x1f202000, base_va 0x1f202000 size 0x8000, attr 0x3
mmap_add_region: base_pa 0x1f202000, base_va 0x1f202000 size 0x4000, attr 0x1
mmap_add_region: base_pa 0x1f20a000, base_va 0x1f20a000 size 0x0, attr 0x2
mmap_add_region: base_pa 0x1f20a000, base_va 0x1f20a000 size 0x4000, attr 0xb
mmap_add_region: base_pa 0x1f200000, base_va 0x1f200000 size 0x800000, attr 0x3
mmap_add_region: base_pa 0xe0000000, base_va 0xe0000000 size 0x800000, attr 0x2
mmap_add_region: base_pa 0x0, base_va 0x0 size 0x1f000000, attr 0x7
NOTICE: TSP: v1.0(debug):ce09c60
NOTICE: TSP: Built : 17:28:06, Sep 7 2015
INFO: TSP: Total memory base : 0x1f202000
INFO: TSP: Total memory size : 0x8000 bytes
INFO: TSP: cpu 0x80000000: 1 smcs, 1 erets 1 cpu on requests
INFO: BL3-1: Preparing for EL3 exit to normal world
INFO: BL3-1: Next image address = 0x11000000
INFO: BL3-1: Next image spsr = 0x3c9

U-Boot 2015.07-geb45d63 (Nov 02 2016 - 17:06:48 +0000)S900 96BOARD, Build: jenkins-96boards-bubblegum-u-boot-10

DRAM: 2 GiB
Relocation Offset is: 6ef48000
Relocating to 7ff48000, new gd at 7df45e08, sp at 7df43cb0
PMU_INFO:found PMIC type 2 ver 3
PMU_INFO:PMU_SYS_CTL0 0xe0d5, CTL1 0x4017, CTL2 0x680, CTL3 0x4000
owl_init_power_status: power_status: 0
clk: core_pll 1104MHz, dev_pll 660MHz, display_pll 1056MHz
MMC: MMC: source clk CMU_DEVPLL:660000000Hz
error: SDC0 send CMD8, No rsp
error: SDC0 send CMD55, No rsp
error: SDC0 send CMD1, No rsp
Card did not respond to voltage select!
host0 scan err
host0 checkout to uartpin
ct2:0x000b4000
MMC: sou`

#2

If I recall correctly there’s a very tight timeout to react to. I generally make sure things are working stabbing the Return key two or three times per second more or less fomr the point I start the ADFU tool running…

#3

Thanks danielt, I have get u-boot source and compiled successful. I would like to debug u-boot for this issue, because I did not see “Hit key to stop autoboot” in above log.

After u-boot compiled, I only get u-boot.dtb.bin but ADFU requires u-boot.dtb.img, do you know how to convert u-boot.dtb.bin to u-boot.dtb.img? Thanks

#4

Sorry for above stupid question, I know that, just use “make u-boot-dtb.img”…

#5

Hi danielt,
After debugging u-boot, I found the reason as below:

 - In u-boot-bugglegum96-2015.07/include/configs/s900_96board.h file, there are two slots defined as 
 `
 #define SLOT0                                          0
 #define SLOT2                                          2
 `
 When executing owl_mmc_init(SLOT2), the u-boot actually got hang.....

 So if change "#define SLOT2" to "#undef SLOT2", system works normal, and I can enter u-boot shell as "owl&gt;".

 The question is whether bubblegum has two MMC slot2? Why u-boot code define SLOT2 for MMC?

Ken

#6

The two slots will for the built-in eMMC and the microSD slot. I’m afraid I cannot remember which is which…

#7

Hi Danielt
Actually SLOT2 is for SDCard…so the linux would not able to boot if I undefine SLOT2…
But if I enabled SLOT2, the message is always stopped at “MMC Sour”, so could not enter u-boot shell or could not get linux kernel boot log from serial console, although Linux still could boot…
It means when detecting SLOT2 or initializing SLOT2, serial output will stop after that…Do not know why? Is there any conflicted between SDcard(SLOT2) and serial output?

K

#8

To be honest I still don’t really understand why enabling/disabling SLOT2 has any effect (unless the BG96 just doesn’t “like” the card you have inserted; is there anything in the slot?).

However, I don’t think any SD card is needed to install Debian. The normal debian install instructions will install to the eMMC.