BLSP as UART crash

I configured BLSP1 as UART and I can’t get the system to boot. Kernel version is qcomlt-4.14. I’m attaching kernel output and patch:

diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
index 25849a17fbe6..2564b14d4365 100644
--- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
@@ -25,6 +25,7 @@
 		serial0 = &blsp2_uart1;
 		serial1 = &blsp2_uart2;
 		serial2 = &blsp1_uart1;
+		serial3 = &blsp1_uart0;
 		i2c0	= &blsp1_i2c2;
 		i2c1	= &blsp2_i2c1;
 		i2c2	= &blsp2_i2c0;
@@ -106,10 +107,18 @@
 			status = "okay";
 		};
 
+		serial@756f000 {
+			label = "LS-UART2";
+			status = "okay";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&blsp1_uart0_default>;
+			pinctrl-1 = <&blsp1_uart0_sleep>;
+		};
+
 		spi@07575000 {
 		/* On Low speed expansion */
 			label = "LS-SPI0";
-			status = "okay";
+			status = "disabled";
 		};
 
 		i2c@075b5000 {
diff --git a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
index 1759e552e3eb..343ee0b9ae00 100644
--- a/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996-pins.dtsi
@@ -93,6 +93,30 @@
 		};
 	};
 
+	blsp1_uart0_default: blsp1_uart0 {
+		pinmux {
+			function = "blsp_uart1";
+			pins = "gpio0", "gpio1";
+		};
+		pinconf {
+			pins = "gpio0", "gpio1";
+			drive-strength = <16>;
+			bias-disable;
+		};
+	};
+
+	blsp1_uart0_sleep: blsp1_uart0_sleep {
+		pinmux {
+			function = "gpio";
+			pins = "gpio0", "gpio1";
+		};
+		pinconf {
+			pins = "gpio0", "gpio1";
+			drive-strength = <2>;
+			bias-disable;
+		};
+	};
+
 	blsp1_i2c2_default: blsp1_i2c2_default {
 		pinmux {
 			function = "blsp_i2c3";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 6dfd248a270e..2a4c852b0cda 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -716,6 +716,16 @@
 			status = "disabled";
 		};
 
+		blsp1_uart0: serial@756f000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x0756f000 0x1000>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+			<&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
 		blsp2_i2c0: i2c@075b5000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			reg = <0x075b5000 0x1000>;
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index 1db79ee8a886..1db20b1c48be 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -1560,6 +1560,15 @@ static struct msm_port msm_uart_ports[] = {
 			.line = 2,
 		},
 	},
+	{
+		.uart = {
+			.iotype = UPIO_MEM,
+			.ops = &msm_uart_pops,
+			.flags = UPF_BOOT_AUTOCONF,
+			.fifosize = 64,
+			.line = 3,
+		},
+	},
 };
 
 #define UART_NR	ARRAY_SIZE(msm_uart_ports)

I have no idea what am I doing wrong. I tried different versions of BSPs and different uSOMs, but the end result is the same. Actually no BLSP works with UART for me, but if I configure BLSP1 as SPI then it boots (so it’s not a TrustZone issue). I also put the uSoM on the development kit board, turned on the neccessary switches on dev board (S10 FORCE USB BOOT on 1 and S1 USB1 MODE SEL on 1) and ran
sudo ./qdl prog_emmc_firehose_8996_ddr.elf rawprogram-820.xml patch.xml
but it did not work.

Does anybody have any advice what should I check and where to look/debug?

I’m affraid you can not be sure, UART_DM and SPI_QUP cores are mapped to different regions in the BLSP (UART0: 0x0756F000 SPI0: 0x7575000).

Try to use devmem2 tool once you booted to check if you are able to read 0x0756F000.

I tried:
$ sudo ./devmem2 0x0756f000
and the kernel crashed with the following dump

[11:27:22:783] <break>
[11:27:22:958] ␍␊
[11:27:22:958] Format: Log Type - Time(microsec) - Message - Optional Info␍␊
[11:27:23:001] Log Type: B - Since Boot(Power On Reset),  D - Delta,  S - Statistic␍␊
[11:27:23:001] S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.0-00306␍␊
[11:27:23:001] S - IMAGE_VARIANT_STRING=M8996LAB␍␊
[11:27:23:001] S - OEM_IMAGE_VERSION_STRING=crm-ubuntu39␍␊
[11:27:23:001] S - Boot Interface: UFS␍␊
[11:27:23:001] S - Secure Boot: Off␍␊
[11:27:23:001] S - Boot Config @ 0x00076044 = 0x000001c9␍␊
[11:27:23:001] S - JTAG ID @ 0x000760f4 = 0x4003e0e1␍␊
[11:27:23:001] S - OEM ID @ 0x000760f8 = 0x00000000␍␊
[11:27:23:001] S - Serial Number @ 0x00074138 = 0x2a579807␍␊
[11:27:23:001] S - OEM Config Row 0 @ 0x00074188 = 0x0000000000000000␍␊
[11:27:23:044] S - OEM Config Row 1 @ 0x00074190 = 0x0000000000000000␍␊
[11:27:23:044] S - Feature Config Row 0 @ 0x000741a0 = 0x0050000010000100␍␊
[11:27:23:044] S - Feature Config Row 1 @ 0x000741a8 = 0x00fff00001ffffff␍␊
[11:27:23:044] S - Core 0 Frequency, 1228 MHz␍␊
[11:27:23:044] B -         0 - PBL, Start␍␊
[11:27:23:044] B -     10413 - bootable_media_detect_entry, Start␍␊
[11:27:23:044] B -     47075 - bootable_media_detect_success, Start␍␊
[11:27:23:044] B -     47079 - elf_loader_entry, Start␍␊
[11:27:23:044] B -     48096 - auth_hash_seg_entry, Start␍␊
[11:27:23:044] B -     48197 - auth_hash_seg_exit, Start␍␊
[11:27:23:044] B -     80120 - elf_segs_hash_verify_entry, Start␍␊
[11:27:23:097] B -     82620 - PBL, End␍␊
[11:27:23:097] B -     84668 - SBL1, Start␍␊
[11:27:23:097] B -    180682 - usb: hs_phy_nondrive_start␍␊
[11:27:23:097] B -    181017 - usb: PLL lock success - 0x3␍␊
[11:27:23:097] B -    184006 - usb: hs_phy_nondrive_finish␍␊
[11:27:23:097] B -    188154 - boot_flash_init, Start␍␊
[11:27:23:097] D -         0 - boot_flash_init, Delta␍␊
[11:27:23:097] B -    195261 - sbl1_ddr_set_default_params, Start␍␊
[11:27:23:097] D -         0 - sbl1_ddr_set_default_params, Delta␍␊
[11:27:23:097] B -    203252 - boot_config_data_table_init, Start␍␊
[11:27:23:209] D -    124531 - boot_config_data_table_init, Delta - (60 Bytes)␍␊
[11:27:23:230] B -    332267 - CDT Version:3,Platform ID:10,Major ID:1,Minor ID:0,Subtype:28␍␊
[11:27:23:230] B -    337025 - Image Load, Start␍␊
[11:27:23:257] D -     22204 - PMIC Image Loaded, Delta - (37368 Bytes)␍␊
[11:27:23:257] B -    359229 - pm_device_init, Start␍␊
[11:27:23:257] B -    365024 - PON REASON:PM0:0x20020 PM1:0x20020 ␍␊
[11:27:23:316] B -    401288 - PM_SET_VAL:Skip␍␊
[11:27:23:316] D -     39894 - pm_device_init, Delta␍␊
[11:27:23:316] B -    403210 - pm_driver_init, Start␍␊
[11:27:23:316] D -      2958 - pm_driver_init, Delta␍␊
[11:27:23:316] B -    409798 - pm_sbl_chg_init, Start␍␊
[11:27:23:316] D -        91 - pm_sbl_chg_init, Delta␍␊
[11:27:23:316] B -    416569 - vsense_init, Start␍␊
[11:27:23:316] D -         0 - vsense_init, Delta␍␊
[11:27:23:316] B -    424377 - Pre_DDR_clock_init, Start␍␊
[11:27:23:316] D -       396 - Pre_DDR_clock_init, Delta␍␊
[11:27:23:316] B -    430172 - ddr_initialize_device, Start␍␊
[11:27:23:316] B -    433862 - 8996 v3.x detected, Max frequency = 1.8 GHz␍␊
[11:27:23:316] B -    440328 - ddr_initialize_device, Delta␍␊
[11:27:23:337] B -    443470 - Basic DDR tests done␍␊
[11:27:24:931] B -   2020716 - clock_init, Start␍␊
[11:27:24:931] D -       244 - clock_init, Delta␍␊
[11:27:24:931] B -   2022729 - Image Load, Start␍␊
[11:27:24:931] D -      6314 - QSEE Dev Config Image Loaded, Delta - (46008 Bytes)␍␊
[11:27:24:931] B -   2029378 - Image Load, Start␍␊
[11:27:24:931] D -      5490 - APDP Image Loaded, Delta - (0 Bytes)␍␊
[11:27:24:963] B -   2058963 - usb: fedl, vbus_low␍␊
[11:27:24:963] B -   2059024 - Image Load, Start␍␊
[11:27:24:963] D -     10645 - XBLRamDump Image Loaded, Delta - (342782 Bytes)␍␊
[11:27:25:017] B -   2124294 - usb: init start␍␊
[11:27:25:017] B -   2126094 - usb: PLL lock success , 0x2␍␊

while for SPI_QUP BLSP 1 it works

 $ sudo ./devmem2 0x07575000
/dev/mem opened.
Memory mapped at address 0xffff9d681000.
Value at address 0x7575000 (0xffff9d681000): 0x2000 

Can I do anything else or is the support the only way to go from here on?

I hate to see you struggling with this, but in this case your answer is in the fine manual. https://www.inforcecomputing.com/public_docs/Qualcomm%20Snapdragon%20410%20APQ8016%20Device%20Specification.pdf Pages 20 and 21.

The 410 processor only has two UARTs, no matter what you try you will never manage to enable a third…

By default the code for the 410c board already has both UARTs enabled.

Oops, correction, this is 820, not 410. All of the 820 BLSPs can run UART. The 820c board build has two enabled by default, I’m not sure what your issue might be.

Might be that he’s not got a db820c, but rather some other board that perhaps has a snapdragon 820c. He refers to a uSoM.

I have Intrinsyc 820uSoM and the development kit for it.

Looks to me like you need to get Intrinsyc to supply you a new firmware with a different TZ config.