After building u-boot from Xilinx, it fail to run in target ultra96v2 board

Products Support Ultra96
#1

I just get a new ultra96v2 board, following the instruction from avnet, I can make a “hello world” project to build a Boot image and make it load from SD card, that means, the FSBL and Bitstream work on the board, I also can print message to the uart 1 in the “hello world” application.
So, my next goal is, build u-boot for the ultra96v2 board.

Following steps I did:

  1. Download the uboot source code from Xilinx GIT site, I use the u-boot code release version 2018.3
  2. Build it by following script in Ubuntu virtual machine , where I installed xilinx sdk version 2018.3
    ----------------------------script start------------------------------------
    UBOOT_DIR=…/u-boot-xlnx-xilinx-v2018.3
    export CROSS_COMPILE=aarch64-linux-gnu-
    export ARCH=arm
    export PATH=$PATH:/tools/Xilinx/SDK/2018.3/gnu/aarch64/lin/aarch64-linux/bin
    make -C $UBOOT_DIR distclean
    make -C $UBOOT_DIR avnet_ultra96_rev1_defconfig
    make -C $UBOOT_DIR
    cp $UBOOT_DIR/u-boot ./u-boot-ultra96.elf
    ------------------------------script end------------------------------------
  3. The build is pass, and I can get the u-boot.elf file
  4. I copy the u-boot.elf to my Windows host,
  5. In Windows version Xilinx SDK, I use the project of “hello world” to “Create Boot Image”, I select the u-boot.elf to make image.
  6. After loading this Boot.bin to sd card, reset the ultra96v2 board, the output on the UART is like below.

So, should I create boot.bin in this way(build u-boot in virtual machine, and make boot image in Windows)? And, if there anything I miss when building the u-boot?

Appreciate of any kind of help, thanks!

---------------The serial output of UART is ----------------------------
“Synchronous Abort” handler, esr 0x5e000000
ELR: 80ad2f4
LR: 7ff7d00
x0 : 00000000c2000001 x1 : 0000000000000000
x2 : 0000000000000000 x3 : 0000000007ff7d30
x4 : 000000000806b7c4 x5 : 0000000007ff7d50
x6 : 000000000806b830 x7 : 0000000000000002
x8 : 000000000000773c x9 : 0000000000000080
x10: 0000000007ff7d6c x11: 000000000809eab0
x12: 00000000000076f0 x13: 0000000000007740
x14: 0000000007ff7dcc x15: 000000000809eab0
x16: 0000000000000000 x17: 0000000000000000
x18: 0000000007ff7ea0 x19: 0000000007ff7e28
x20: 00000000080a6000 x21: 0000000000000000
x22: 0000000000000004 x23: 00000000fffd71b8
x24: 0000000000000100 x25: 0000000000000100
x26: 00000000000fc5c8 x27: 000000000056a3c0
x28: 0000000000000010 x29: 0000000007ff7cd0

Resetting CPU …
---------------------------------The serial output of UART end-------------------------------------------

image
image764×898 66.3 KB

#2

./board/xilinx/zynqmp/zynqmp-zcu100-revC/psu_init_gpl.c
./arch/arm/include/asm/arch-zynqmp/psu_init_gpl.h

I also replace above two files, but they looks like have no relation, as I did not use linux version SDK to create FSBL, I use Windows version SDK to create SDK.

Btw, the ultrav1, v2 and zynqmp-zcu100-revC are compatible boards, so when building u-boot for ultra96v2, the configure of ultra96v1 is used, in configure of ultra96v1, the zcu100 is referenced.

#3

have not fix the problem, please advise.

#4

I suggest you take a look at the posted PetaLinux BSP at www.avnet.me/ultra96-v2 → Reference Designs.

You could also consider taking the PetaLinux course at www.avnet.me/ttc_on_demand.

Bryan